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Thu, 22 Oct 2026 12:31:20 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Thu, 22 Oct 2026 12:31:15 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Bjorn Helgaas , Carolina Jubran , Cosmin Ratiu , Edward Srouji , "Gal Pressman" , Jason Gunthorpe , Kees Cook , Leon Romanovsky , open list , , , Maher Sanalla , Mark Bloch , Or Har-Toov , Saeed Mahameed , Shay Drori , Tariq Toukan Subject: [PATCH net V2 1/4] {RDMA,net}/mlx5: cache and use TX-enabled aggregate speed for vports Date: Thu, 22 Oct 2026 22:30:50 +0300 Message-ID: <20261022193053.3815866-2-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261022193053.3815866-1-tariqt@nvidia.com> References: <20261022193053.3815866-1-tariqt@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN7PEPF00000091:EE_|DM4PR12MB6229:EE_ X-MS-Office365-Filtering-Correlation-Id: a7260561-a346-4e5a-28b5-08df30731cc2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|7416014|36860700016|376014|23010399003|82310400026|56012099006|261021135927099003|261009223027099003|11063799006|22082099003|261021123027099003|6133799003|261021121427099003|13003099007|18002099003|10067099003|260925021911599003|260925022911599003|261022105027099003|260925021311599003; X-Microsoft-Antispam-Message-Info: cN2Ta6QDz484/7rRNyG2i4NwIbPIew03a4uYhSESOURvkOSyUkYL4mdNJFueZ3d9XHJLqGZnIk87LT2VXru7GB6IPb5FPElpdcZaDd1D/4vOvAOPxvS3ZLyXAkpk3mLtDghX1TiB579kZkOgE4fe1J3gyd+xgbWK4HLwn4yctOi8rvDT0dk9yqM4ivLmkYYS4Q3A+kewQ4vztgGcTAoKVIQUkCF+2zJuN8aG3ZvIxp645QUkegc9uJHBro0D1401HjCKpQZd9ZfyBIN7zV8i3hKvfq0aL86RVsEbBYse4x6VE5sDCWkVtaDvXVU4bfvIdiMSOn4ONLtlAt3h5Sy9suGfOgFi+8gY92mPVs52UXQb0S6KaHwilJZlYC0f6BQF0z7Aj/7g9f8SCLlS9IInNkfkx84Gl5Lx7Lnw/OyZtqTL0Jr4acs57aKX3AAfi29IBFf4sECzwiDvWwmbiVp7cEa+8BUH4l9Z+fYrkC2ZGoZFQFD8i/B+4hzZUhIFtNflRrAQUM7CVuZSA6PDpvpAK9V5GLTu6jjpq99j2Tf613yVhFG71LJyJ4rqXSZ3QhiM9Ycl4afFBMnD0Q2zCI2txiOFbwELAXjHQRmYvUqOSmVBgQ9NDBxIffS3CvkadPRdEwtgdASwXCxOFL+VJ1sbkh1O1hDXP8fCEgk0M8q9Agpa4TPFe0GEM5ZoYzpbAvCLQ727501O7kvo/ruQIRm4mw== X-Forefront-Antispam-Report: CIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(36860700016)(376014)(23010399003)(82310400026)(56012099006)(261021135927099003)(261009223027099003)(11063799006)(22082099003)(261021123027099003)(6133799003)(261021121427099003)(13003099007)(18002099003)(10067099003)(260925021911599003)(260925022911599003)(261022105027099003)(260925021311599003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 97ogMiXYBA63fZg9EBZgfqASU7aTeAaTG6WhCgxJl8MYpEy6YKN95Ojh9XuAy9ydlH7YT/UsRS+PYehQ1wIWr4w1D/JzG+FtWfyVGMldLxVpy+it3VzS/KGgkKRTJ7kfTlY8TELDSOHz0ZfYAa3fQ+SA7TO3OVzrAqLfccu1EEkiG427oN0ejBZf3kBqzXAZu2bg0gTXMVRRrQVZb5gj2uidnMbRVpiP1DjF3OUeJEntp8sgxkukx09reEiZMxuJulxFVnBRe2RHWj9IkZmyfGoxltwLdI77R8W2MNwfMLaNEzommsqD2STbdyVxg9WSd9cOseI+DRbX2ymFF9C4o4z+FDuqDC0qppU28Z2HGGzGCPg1WkYzGOVSYTffemWdl6uyxk5fKeNxkdK0zJW2P5A9pOMwLqyvZRwhtaVRQ76JokbZpL5+9JsoAcKKfjo3 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2026 19:31:46.9947 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a7260561-a346-4e5a-28b5-08df30731cc2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN7PEPF00000091.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6229 From: Or Har-Toov Cache aggregate TX-enabled speed we calculated, and use it instead of querying the bond speed so we can, in the following patch, limit it by the PCI bandwidth. The bond speed takes the calculation from PTYS, and PTYS is not bounded by the PCI bandwidth of the NIC. The max-speed fallback in mlx5_lag_set_vports_agg_speed() is local to VF/SF vport rate-limit programming; agg_speed_mbps stores operational speed only, and mlx5_lag_query_aggregated_speed() correctly returns zero when all member links are down. Until the aggregate has been measured, or after a failed measurement, mlx5_lag_query_aggregated_speed() returns -ENODATA. Fixes: 50f1d188c580 ("net/mlx5: Propagate LAG effective max_tx_speed to vports") Signed-off-by: Or Har-Toov Reviewed-by: Mark Bloch Reviewed-by: Shay Drori Signed-off-by: Tariq Toukan --- drivers/infiniband/hw/mlx5/main.c | 2 +- .../net/ethernet/mellanox/mlx5/core/esw/qos.c | 1 + .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 86 +++++++++++++++---- .../net/ethernet/mellanox/mlx5/core/lag/lag.h | 16 +++- include/linux/mlx5/driver.h | 2 +- 5 files changed, 84 insertions(+), 23 deletions(-) v1: https://lore.kernel.org/all/20260910102432.3845360-4-tariqt@nvidia.com/ Changes in v2: - Count only TX-enabled, link-up ports from the LAG tracker for non-MPESW modes; MPESW keeps the vport state check - mlx5_lag_update_agg_speed() returns an error, and mlx5_lag_set_vports_agg_speed() bails out on failure instead of using the previous cached speed; the #else stub checks the return too - Stop exporting mlx5_lag_query_bond_speed(), which has no users outside mlx5_core - Describe in the changelog what mlx5_lag_query_aggregated_speed() returns when all member links are down - Start agg_speed_mbps as SPEED_UNKNOWN and reset it to SPEED_UNKNOWN on teardown; mlx5_lag_query_aggregated_speed() returns -ENODATA instead of a zero speed until the first successful measurement - A failed measurement invalidates the cached speed diff --git a/drivers/infiniband/hw/mlx5/main.c b/drivers/infiniband/hw/mlx5/main.c index a457647edacd..6594d38cf199 100644 --- a/drivers/infiniband/hw/mlx5/main.c +++ b/drivers/infiniband/hw/mlx5/main.c @@ -1654,7 +1654,7 @@ static int mlx5_ib_query_port_speed_from_bond(struct mlx5_ib_dev *dev, u32 bond_speed; int err; - err = mlx5_lag_query_bond_speed(mdev, &bond_speed); + err = mlx5_lag_query_aggregated_speed(mdev, &bond_speed); if (err) return err; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c index 0d20f51b9702..0148306421ad 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/esw/qos.c @@ -5,6 +5,7 @@ #include "lib/mlx5.h" #include "esw/qos.h" #include "en/port.h" +#include "lag/lag.h" #define CREATE_TRACE_POINTS #include "diag/qos_tracepoint.h" diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index 4e173b08cb37..57755ceab8a7 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -360,6 +360,7 @@ static struct mlx5_lag *mlx5_lag_dev_alloc(struct mlx5_core_dev *dev) ldev->ports = MLX5_CAP_GEN(dev, num_lag_ports); ldev->buckets = 1; + ldev->agg_speed_mbps = SPEED_UNKNOWN; return ldev; } @@ -1431,10 +1432,10 @@ static bool mlx5_lag_should_disable_lag(struct mlx5_lag *ldev, bool do_bond) ldev->mode != MLX5_LAG_MODE_MPESW; } -#ifdef CONFIG_MLX5_ESWITCH static int mlx5_lag_get_devices_oper_speed(struct mlx5_lag *ldev, u32 *sum_speed) { + bool mpesw = ldev->mode == MLX5_LAG_MODE_MPESW; int pf_idx; *sum_speed = 0; @@ -1452,15 +1453,21 @@ static int mlx5_lag_get_devices_oper_speed(struct mlx5_lag *ldev, pf_mdev = pf->dev; if (!pf_mdev) continue; - ret = mlx5_query_vport_max_tx_speed(pf_mdev, opmod, 0, 0, - &speed, &state); - if (ret) { - mlx5_core_dbg(pf_mdev, "State query failed (err=%d)\n", - ret); - return ret; - } - if (state != VPORT_STATE_UP) + if (mpesw) { + ret = mlx5_query_vport_max_tx_speed(pf_mdev, opmod, 0, + 0, &speed, &state); + if (ret) { + mlx5_core_dbg(pf_mdev, + "State query failed (err=%d)\n", + ret); + return ret; + } + if (state != VPORT_STATE_UP) + continue; + } else if (!ldev->tracker.netdev_state[pf_idx].tx_enabled || + !ldev->tracker.netdev_state[pf_idx].link_up) { continue; + } ret = mlx5_port_oper_linkspeed(pf_mdev, &speed); if (ret) { @@ -1476,6 +1483,31 @@ static int mlx5_lag_get_devices_oper_speed(struct mlx5_lag *ldev, return 0; } +int mlx5_lag_update_agg_speed(struct mlx5_lag *ldev) +{ + u32 speed; + int err; + + lockdep_assert_held(&ldev->lock); + + err = mlx5_lag_get_devices_oper_speed(ldev, &speed); + if (err) { + WRITE_ONCE(ldev->agg_speed_mbps, SPEED_UNKNOWN); + return err; + } + + WRITE_ONCE(ldev->agg_speed_mbps, speed); + return 0; +} + +void mlx5_lag_reset_agg_speed(struct mlx5_lag *ldev) +{ + lockdep_assert_held(&ldev->lock); + + WRITE_ONCE(ldev->agg_speed_mbps, SPEED_UNKNOWN); +} + +#ifdef CONFIG_MLX5_ESWITCH static int mlx5_lag_get_devices_max_speed(struct mlx5_lag *ldev, u32 *max_speed) { bool take_max; @@ -1559,19 +1591,18 @@ void mlx5_lag_set_vports_agg_speed(struct mlx5_lag *ldev) u32 speed; int pf_idx; - if (ldev->mode == MLX5_LAG_MODE_MPESW) { - if (mlx5_lag_get_devices_oper_speed(ldev, &speed)) - return; - } else { - speed = ldev->tracker.bond_speed_mbps; - if (speed == SPEED_UNKNOWN) - return; - } + if (mlx5_lag_update_agg_speed(ldev)) + return; + + speed = ldev->agg_speed_mbps; - /* If speed is not set, fall back to the max achievable speed */ + /* If speed is 0, fallback to the max speed */ if (!speed && mlx5_lag_get_devices_max_speed(ldev, &speed)) return; + if (!speed) + return; + speed = speed / MLX5_MAX_TX_SPEED_UNIT; mlx5_ldev_for_each(pf_idx, 0, ldev) { @@ -1594,6 +1625,7 @@ void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev) int pf_idx; int ret; + mlx5_lag_reset_agg_speed(ldev); mlx5_ldev_for_each(pf_idx, 0, ldev) { pf = mlx5_lag_pf(ldev, pf_idx); if (!pf) @@ -2089,6 +2121,23 @@ static int mlx5_handle_changeinfodata_event(struct mlx5_lag *ldev, return 1; } +/* Returns speed in Mbps. */ +int mlx5_lag_query_aggregated_speed(struct mlx5_core_dev *mdev, u32 *speed) +{ + struct mlx5_lag *ldev; + + ldev = mlx5_lag_dev(mdev); + if (!ldev) + return -ENODEV; + + *speed = READ_ONCE(ldev->agg_speed_mbps); + if (*speed == SPEED_UNKNOWN) + return -ENODATA; + + return 0; +} +EXPORT_SYMBOL_GPL(mlx5_lag_query_aggregated_speed); + static void mlx5_lag_update_tracker_speed(struct lag_tracker *tracker, struct net_device *ndev) { @@ -2146,7 +2195,6 @@ int mlx5_lag_query_bond_speed(struct mlx5_core_dev *mdev, u32 *speed) spin_unlock_irqrestore(&lag_lock, flags); return ret; } -EXPORT_SYMBOL_GPL(mlx5_lag_query_bond_speed); /* this handler is always registered to netdev events */ static int mlx5_lag_netdev_event(struct notifier_block *this, diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h index e9f0ef83ce1d..45b0e8fd8f99 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.h @@ -99,6 +99,7 @@ struct mlx5_lag { /* Protect lag fields/state changes */ struct mutex lock; struct lag_mpesw lag_mpesw; + u32 agg_speed_mbps; }; static inline struct mlx5_lag * @@ -258,12 +259,23 @@ void mlx5_lag_rescan_dev_locked(struct mlx5_lag *ldev, void mlx5_lag_add_devices_filter(struct mlx5_lag *ldev, u32 filter); struct mlx5_devcom_comp_dev *mlx5_lag_get_devcom_comp(struct mlx5_lag *ldev); +int mlx5_lag_update_agg_speed(struct mlx5_lag *ldev); +void mlx5_lag_reset_agg_speed(struct mlx5_lag *ldev); +int mlx5_lag_query_bond_speed(struct mlx5_core_dev *dev, u32 *speed); + #ifdef CONFIG_MLX5_ESWITCH void mlx5_lag_set_vports_agg_speed(struct mlx5_lag *ldev); void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev); #else -static inline void mlx5_lag_set_vports_agg_speed(struct mlx5_lag *ldev) {} -static inline void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev) {} +static inline void mlx5_lag_set_vports_agg_speed(struct mlx5_lag *ldev) +{ + mlx5_lag_update_agg_speed(ldev); +} + +static inline void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev) +{ + mlx5_lag_reset_agg_speed(ldev); +} #endif static inline bool mlx5_lag_is_supported(struct mlx5_core_dev *dev) diff --git a/include/linux/mlx5/driver.h b/include/linux/mlx5/driver.h index 83d0a83bbfbc..ff38086c6c56 100644 --- a/include/linux/mlx5/driver.h +++ b/include/linux/mlx5/driver.h @@ -1154,7 +1154,7 @@ int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); bool mlx5_lag_is_active(struct mlx5_core_dev *dev); -int mlx5_lag_query_bond_speed(struct mlx5_core_dev *dev, u32 *speed); +int mlx5_lag_query_aggregated_speed(struct mlx5_core_dev *dev, u32 *speed); bool mlx5_lag_mode_is_hash(struct mlx5_core_dev *dev); bool mlx5_lag_is_master(struct mlx5_core_dev *dev); bool mlx5_lag_is_shared_fdb(struct mlx5_core_dev *dev); -- 2.44.0