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Thu, 22 Oct 2026 12:31:36 -0700 Received: from vdi.nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.182) with Microsoft SMTP Server id 15.2.2562.56 via Frontend Transport; Thu, 22 Oct 2026 12:31:31 -0700 From: Tariq Toukan To: Andrew Lunn , "David S. Miller" , Eric Dumazet , Jakub Kicinski , , Paolo Abeni CC: Bjorn Helgaas , Carolina Jubran , Cosmin Ratiu , Edward Srouji , "Gal Pressman" , Jason Gunthorpe , Kees Cook , Leon Romanovsky , open list , , , Maher Sanalla , Mark Bloch , Or Har-Toov , Saeed Mahameed , Shay Drori , Tariq Toukan Subject: [PATCH net V2 4/4] net/mlx5: Lag, save and restore vport max_tx_speed across LAG Date: Thu, 22 Oct 2026 22:30:53 +0300 Message-ID: <20261022193053.3815866-5-tariqt@nvidia.com> X-Mailer: git-send-email 2.44.0 In-Reply-To: <20261022193053.3815866-1-tariqt@nvidia.com> References: <20261022193053.3815866-1-tariqt@nvidia.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH7PEPF00000008:EE_|PH7PR12MB9075:EE_ X-MS-Office365-Filtering-Correlation-Id: 03e23519-1faa-4df6-cc88-08df30732376 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|23010399003|376014|82310400026|1800799024|36860700016|13003099007|261021121427099003|11063799006|261021123027099003|56012099006|261009223027099003|10067099003|18002099003|261022105027099003|22082099003; X-Microsoft-Antispam-Message-Info: k5ktK6KXEK26Bm5Jv01Sw34Bw6ThW3xPDyx4ax08nd7Ix07OeEZ8tPzJuBX1eJ0qwvDwNPE+ewBT+gDjWVVUCvp9o4dfWzkwZP4Ym1rLXWnAA1VEYmxAGAC1SIo87Rh/RWw05xsLtcMjn6ew9YiGsMyksVphh7+sC3xRUzgD6UQ8GOMV5G2c/jMeYEiuBcqWSUaXNrOWueLr2g+7wMtotngsSlE5pq5urcQhjzAg1ZUr94UgCmr1Vhd6xUAAGh2twU3wiXD9FcUdWSoHX/vVnA+mwDsKNMhPsm5256ZnUvUhpYtVjspCCIt9/LZkG2TphPjlSZpyEYWjioBw4W7OoTy5XLKXkvEJyMkbrdUNVBIbIbuNZozBLP8kVTD4nfmqw3nQQ7zKbIzANxU0zvcuP029VKAANW3IGOtWkvGA8eV0+iab5D15QalCmtor1EjNqDwpXEaWRYuTOPRHUEHNiFOcgOzVdQNw+Tf72YPXpTxGQvaVmyyEKGUMThpURYTrQQBbX7tkAVMpIuFnFECa1a/lzrVKd8kArTheMtcCObILodGL8nR6JNzfggft8DbXZIdYCqdHWOjkQR7GUopXqWpRGtkxUjHuua566bqFGM0Zto2IcTnofljihzfXQVlmK4WvpS/mUPHkP2k86u6QfqVFaO31FvaEoiUSVY8TlCKm4z+q6cnXVFFX9JKmAvBE1Q7Vgr/YO6yr8I00gkCIuA== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(7416014)(23010399003)(376014)(82310400026)(1800799024)(36860700016)(13003099007)(261021121427099003)(11063799006)(261021123027099003)(56012099006)(261009223027099003)(10067099003)(18002099003)(261022105027099003)(22082099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: kUZ+QsQxbu8seF8IwStOen3x3ocf8I3NzVndPLvGfIB0oLrnDxLQztyagUHnIXQeaUZikc/77KaXmEJ4mYAnLgh6ta1paAltZ3T/17R79Not3f5DqqIkDXpDoakLSk6bRTiBz/CJy1fbvtjJp0bp6zHnBYgS2k8S0uSIABZZh9Q8L8WYMTmb3GOVTo4GFGPNELj4TQ6nbS2ZkAVgP2aWvXa643PpYizZZUKlaNk72KMcJJSEzNuKj3B/zSRfZ+2cnriwRoGmC7ZiUpwBlge3aNsAuwfq+zsfwYygx6qUg4BoabewKeTWMjw3/WxmvIojEDah36dgdG7+0jrX0jx7Njne5EtqobhYovHmXTUSuzZYUgphQ+LH5aqxOxKtmCINL0klJlEMH8wfMFREEmFrxA6ksseoNMed58strXhlQXAvJbm1e2fmDqK7oYk+M9Ex X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2026 19:31:58.3354 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 03e23519-1faa-4df6-cc88-08df30732376 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: PH7PEPF00000008.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB9075 From: Or Har-Toov mlx5_lag_reset_vports_speed() queries the oper link speed at LAG teardown and writes it back to each vport. When the link is down at that moment, mlx5_port_oper_linkspeed() returns 0, which FW treats as "not provided" and ignores, leaving the aggregate rate limit on the vports after teardown. Save each vport's max_tx_speed when the vport is enabled, before the LAG aggregate or a deferred aggregate replay can overwrite it. While a LAG is active, only a vport with a pending aggregate is saved, as FW may already hold the aggregate for any other vport. Restore the saved value per vport at teardown instead of querying the oper speed, and update agg_max_tx_speed to the pre-LAG value so disabled vports replay the correct rate when they are later enabled. A vport keeps its saved value after teardown, as it is the baseline for the next LAG, and for a disabled vport it is also the pending restore value. If the max_tx_speed of a vport could not be saved, it stays zero and mlx5_lag_get_restore_speed() falls back to a link-derived speed at teardown. The aggregate is still applied to such a vport. This also covers the case where the oper speed query fails and the PF is skipped entirely, leaving the aggregate in FW and in agg_max_tx_speed, as raised in the AI review of v1 of "net/mlx5: Lag, reset vport speed on teardown". It is unrelated to that patch, so it is fixed here separately. Firmware never returns zero as a configured max_tx_speed; zero means "not supported", so using it as a sentinel for "not yet saved" is safe. A vport disabled for the entire LAG period was never assigned a per-vport rate limit, so no original speed exists to restore; deferring through agg_max_tx_speed on re-enable is correct. Fixes: 50f1d188c580 ("net/mlx5: Propagate LAG effective max_tx_speed to vports") Link: https://lore.kernel.org/all/20260915015118.875210-1-kuba@kernel.org/ Signed-off-by: Or Har-Toov Reviewed-by: Mark Bloch Signed-off-by: Tariq Toukan --- .../net/ethernet/mellanox/mlx5/core/eswitch.c | 22 ++++++ .../net/ethernet/mellanox/mlx5/core/eswitch.h | 1 + .../net/ethernet/mellanox/mlx5/core/lag/lag.c | 68 ++++++++++++++++--- 3 files changed, 81 insertions(+), 10 deletions(-) diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c index fc197d1dc9df..7cf9c15ec65d 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.c @@ -935,6 +935,27 @@ static void esw_vport_cleanup(struct mlx5_eswitch *esw, struct mlx5_vport *vport esw_vport_cleanup_acl(esw, vport); } +static void mlx5_esw_vport_save_max_tx_speed(struct mlx5_eswitch *esw, + struct mlx5_vport *vport) +{ + u16 op_mod = MLX5_VPORT_STATE_OP_MOD_ESW_VPORT; + int ret; + + if (!MLX5_CAP_ESW(esw->dev, esw_vport_state_max_tx_speed) || + vport->vport == MLX5_VPORT_UPLINK || vport->max_tx_speed) + return; + + if (mlx5_lag_is_active(esw->dev) && !vport->agg_max_tx_speed) + return; + + ret = mlx5_query_vport_max_tx_speed(esw->dev, op_mod, vport->vport, + true, &vport->max_tx_speed, NULL); + if (ret) + mlx5_core_dbg(esw->dev, + "Failed to save vport %d max tx speed, err=%d\n", + vport->vport, ret); +} + static void mlx5_esw_vport_set_max_tx_speed(struct mlx5_eswitch *esw, struct mlx5_vport *vport) { @@ -999,6 +1020,7 @@ int mlx5_esw_vport_enable(struct mlx5_eswitch *esw, struct mlx5_vport *vport, esw->enabled_vports++; esw_debug(esw->dev, "Enabled VPORT(%d)\n", vport_num); + mlx5_esw_vport_save_max_tx_speed(esw, vport); if (vport->agg_max_tx_speed) mlx5_esw_vport_set_max_tx_speed(esw, vport); done: diff --git a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h index 8b1f93b13ea9..3717fb6de0b6 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h +++ b/drivers/net/ethernet/mellanox/mlx5/core/eswitch.h @@ -261,6 +261,7 @@ struct mlx5_vport { int index; struct mlx5_devlink_port *dl_port; u32 agg_max_tx_speed; + u32 max_tx_speed; }; struct mlx5_esw_indir_table; diff --git a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c index afe0b9909f2d..3e623c96b2a1 100644 --- a/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c +++ b/drivers/net/ethernet/mellanox/mlx5/core/lag/lag.c @@ -1712,11 +1712,37 @@ void mlx5_lag_set_vports_agg_speed(struct mlx5_lag *ldev) } } +static int mlx5_lag_get_restore_speed(struct mlx5_core_dev *mdev, + struct mlx5_vport *vport, u32 *speed) +{ + u32 pci_bw; + + if (vport->max_tx_speed) { + *speed = vport->max_tx_speed; + return 0; + } + + *speed = 0; + mlx5_port_oper_linkspeed(mdev, speed); + if (!*speed && mlx5_port_max_linkspeed(mdev, speed)) + return -ENODATA; + + pci_bw = pcie_bandwidth_mbps(mdev->pdev); + if (pci_bw) + *speed = min(*speed, pci_bw); + *speed /= MLX5_MAX_TX_SPEED_UNIT; + return 0; +} + void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev) { + u16 op_mod = MLX5_VPORT_STATE_OP_MOD_ESW_VPORT; struct mlx5_core_dev *mdev; + struct mlx5_eswitch *esw; + struct mlx5_vport *vport; struct lag_func *pf; - u32 speed; + u32 restore_speed; + unsigned long i; int pf_idx; int ret; @@ -1728,17 +1754,39 @@ void mlx5_lag_reset_vports_speed(struct mlx5_lag *ldev) mdev = pf->dev; if (!mdev) continue; - - ret = mlx5_port_oper_linkspeed(mdev, &speed); - if (ret) { - mlx5_core_dbg(mdev, - "Failed to reset vports speed for device %s. Oper speed is not available (err=%d)\n", - dev_name(mdev->device), ret); + esw = mdev->priv.eswitch; + if (!esw || !MLX5_CAP_ESW(mdev, esw_vport_state_max_tx_speed)) continue; - } - speed = speed / MLX5_MAX_TX_SPEED_UNIT; - mlx5_lag_modify_device_vports_speed(mdev, speed); + mutex_lock(&esw->state_lock); + mlx5_esw_for_each_vport(esw, i, vport) { + if (!vport || vport->vport == MLX5_VPORT_UPLINK) + continue; + + if (!vport->enabled) { + vport->agg_max_tx_speed = vport->max_tx_speed; + continue; + } + + if (mlx5_lag_get_restore_speed(mdev, vport, + &restore_speed)) { + vport->agg_max_tx_speed = 0; + continue; + } + + ret = mlx5_modify_vport_max_tx_speed(mdev, op_mod, + vport->vport, + true, + restore_speed); + if (ret) { + mlx5_core_dbg(mdev, + "Failed to restore vport %d max tx speed, err=%d\n", + vport->vport, ret); + continue; + } + vport->agg_max_tx_speed = 0; + } + mutex_unlock(&esw->state_lock); } } #endif -- 2.44.0