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The workaround addresses a hardware defect where the upper address bits of the ARADDR and ACADDR buses within the Cortex-A53 subsystem were incorrectly connected, causing TLBI and IC maintenance operations exchanged between the A53 and A72 clusters to be corrupted. Before the software workaround was available, affected board DTS files worked around this at the DT level by removing the Cortex-A72 CPU nodes (cpu@100, cpu@101), the cpu-map topology, and associated cpu1-thermal zones, effectively running the SoC as a single A53-only cluster. With the kernel-side fix now in place, this series removes the DT-level workarounds and restores full SMP support with both A53 and A72 clusters. The PMIC thermal cooling-device maps are also updated to include A72_0 and A72_1 so both clusters participate in thermal management. Signed-off-by: Peng Fan --- Changes in v2: - patch 1: update PMIC thermal cooling-device map to include A72_0/A72_1 - patch 2: replace manual DT node deletion removal with a proper revert of commit 5d20f1ccb339 ("arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster"), which also restores the cpu1-thermal zone in imx8qm-tqma8qm-mba8x.dts as originally intended - Link to v1: https://patch.msgid.link/20261022-8qm-v1-0-2a597cb3debd@nxp.com --- Peng Fan (2): arm64: dts: imx8qm-mek: Re-enable A72 cluster after ERR050104 workaround Revert "arm64: dts: imx8qm-tqma8qm-mba8x: Disable Cortex-A72 cluster" arch/arm64/boot/dts/freescale/imx8qm-mek.dts | 14 ++------ .../boot/dts/freescale/imx8qm-tqma8qm-mba8x.dts | 39 ++++++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm-tqma8qm.dtsi | 13 ++------ 3 files changed, 45 insertions(+), 21 deletions(-) --- base-commit: 4403278e4ea2f654f8130a5c03eb8b4516a0f201 change-id: 20261022-8qm-875d0b4b3e7d Best regards, -- Peng Fan