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Replace devm_clk_get_enabled() with devm_clk_get_optional_enabled(), and remove FSL_EDMA_DRV_HAS_DMACLK flag to simplify clock handling. Prepare to add channel runtime pm support. Reviewed-by: Frank Li Signed-off-by: Joy Zou --- Changes for v7: - Replace devm_clk_get_optional() with devm_clk_get_optional_enable(). Changes for v6: - Replace devm_clk_get_optional_enable() with devm_clk_get_optional() and devm_clk_prepare_enable() in order to use runtime PM for power management later. - Modify the commit message. - Add Reviewed-by tag. - Link to v5: https://lore.kernel.org/imx/20260513-b4-b4-edma-runtime-opt-v5-0-1e595bfb8423@nxp.com/ --- drivers/dma/fsl-edma-common.h | 1 - drivers/dma/fsl-edma-main.c | 22 ++++++++++------------ 2 files changed, 10 insertions(+), 13 deletions(-) diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 4332b2b2e1df..97b3a9872e90 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -207,7 +207,6 @@ struct fsl_edma_desc { struct fsl_edma_sw_tcd tcd[]; }; -#define FSL_EDMA_DRV_HAS_DMACLK BIT(0) #define FSL_EDMA_DRV_MUX_SWAP BIT(1) #define FSL_EDMA_DRV_CONFIG32 BIT(2) #define FSL_EDMA_DRV_WRAP_IO BIT(3) diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index a85bebc25217..bc94554bc36c 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -559,7 +559,7 @@ static struct fsl_edma_drvdata imx7ulp_data = { .dmamuxs = 1, .chreg_off = EDMA_TCD, .chreg_space_sz = sizeof(struct fsl_edma_hw_tcd), - .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_CONFIG32, + .flags = FSL_EDMA_DRV_CONFIG32, .setup_irq = fsl_edma2_irq_init, }; @@ -572,7 +572,7 @@ static struct fsl_edma_drvdata imx8qm_data = { }; static struct fsl_edma_drvdata imx8ulp_data = { - .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3, + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_EDMA3, .chreg_space_sz = 0x10000, .chreg_off = 0x10000, .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), @@ -581,14 +581,14 @@ static struct fsl_edma_drvdata imx8ulp_data = { }; static struct fsl_edma_drvdata imx93_data3 = { - .flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_ERRIRQ_SHARE, + .flags = FSL_EDMA_DRV_EDMA3 | FSL_EDMA_DRV_ERRIRQ_SHARE, .chreg_space_sz = 0x10000, .chreg_off = 0x10000, .setup_irq = fsl_edma3_irq_init, }; static struct fsl_edma_drvdata imx93_data4 = { - .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_EDMA4 | FSL_EDMA_DRV_ERRIRQ_SHARE, .chreg_space_sz = 0x8000, .chreg_off = 0x10000, @@ -598,7 +598,7 @@ static struct fsl_edma_drvdata imx93_data4 = { }; static struct fsl_edma_drvdata imx95_data5 = { - .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 | + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_EDMA4 | FSL_EDMA_DRV_TCD64 | FSL_EDMA_DRV_ERRIRQ_SHARE, .chreg_space_sz = 0x8000, .chreg_off = 0x10000, @@ -738,13 +738,11 @@ static int fsl_edma_probe(struct platform_device *pdev) regs = &fsl_edma->regs; } - if (drvdata->flags & FSL_EDMA_DRV_HAS_DMACLK) { - fsl_edma->dmaclk = devm_clk_get_enabled(&pdev->dev, "dma"); - if (IS_ERR(fsl_edma->dmaclk)) - return dev_err_probe(&pdev->dev, - PTR_ERR(fsl_edma->dmaclk), - "Missing DMA block clock.\n"); - } + fsl_edma->dmaclk = devm_clk_get_optional_enabled(&pdev->dev, "dma"); + if (IS_ERR(fsl_edma->dmaclk)) + return dev_err_probe(&pdev->dev, + PTR_ERR(fsl_edma->dmaclk), + "Failed to get/enable DMA clock.\n"); ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2); -- 2.34.1