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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 586e51a60fabf-4a8431c012esm226213fac.11.2026.10.23.15.41.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 15:41:08 -0700 (PDT) From: James Hilliard Subject: [PATCH v4 0/4] serial: 8250: serialize DMA cancellation with buffer reuse Date: Fri, 23 Oct 2026 16:41:05 -0600 Message-Id: <20261023-submit-serial-8250-dma-cancel-v1-v4-0-e759de1839de@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/42Sy47bMAxFfyXwum5F6kVl1f8oZkFJ5MRFHq2dC aYY5N/LJF0kAxQI4A0N3nN5SX0Mi8yTLMN69THMcpqW6bC3InxZDW3D+1cZp271gA4TOIRxeau 76TheZLwdCaMb+47Hxvsm2/EEY0VHSkGoNBgM82sWnd6vFj9ebrUxfko7XriXjsqLjHU2wubyy xpm+f3tfw74D2o9bzbu8Ua+QdphZ8OtVwAUlLJgLk6ItVTxAEmTo45CqYZcsOd+RfGxbSzleuW TC1WZPUNDCKXkLqBgQqwEHGIA1sj1UZVL76541eqjYAxint0qIspq/VBT0BLyo4ocR5egU2guR k6h5WQrJpUqHXJpiXItRT959VqDDckKSgkKYdPEoeYYuy9NpcVAiP5RFRyROQFjrpaNLQk6by5 gKS2vIpScEw2X82ym5XiY/1wfxAmuq33+9va5UVRsX0XRO//9dcfT9qvd5Qq3490B8QkgGtDGF 44gngp8Bvp7oH8C6A3YM2mR0ELxeA88n89/AcMsudoRAwAA X-Change-ID: 20261021-submit-serial-8250-dma-cancel-v1-b208f84e89c1 To: Greg Kroah-Hartman , Jiri Slaby , Raul E Rangel , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Andy Shevchenko , Heikki Krogerus , Tony Lindgren , Sebastian Andrzej Siewior Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, James Hilliard X-Mailer: b4 0.15.2 Reserve canceled transmit and receive storage until DMA and its completion callbacks have retired. Serial-core write backpressure protects a flushed TX FIFO while normal transfers continue to DMA directly from that FIFO. The series first separates OMAP's locked completion processing, then adds the serial-core reservation helpers and applies them to 8250 TX. Flushing empties the logical queue immediately. While the old transfer owns its storage, write_room() reports zero and write-ready notifications wait for retirement. Failed termination retains the reservation until normal completion, without advancing the reset FIFO. Shutdown retains any TX reservation until reopen or successful resume makes the port writable. RX delivers paused data before the PIO fallback and retires callbacks in process context. Track FIFO access separately from buffer retirement so PIO and the DesignWare empty-FIFO timeout handling can run once DMA has released the FIFO. On failure, retain the requested interrupt enables in the existing IER shadow and mask receive interrupts in hardware until DMA has stopped. Recovery then leaves RX on PIO until reopen. Shutdown excludes new retirement work before releasing the channels. Based on tty-next with the posted shutdown guard [0], channel configuration error handling [1], RX TTY accounting fix [2], RZ/N1 transfer-length fix [3], and transmit-PM shutdown fix [4]. [0] https://lore.kernel.org/r/20261021-submit-serial-8250-dma-shutdown-v1-v1-1-3d3ce383c614@gmail.com [1] https://lore.kernel.org/r/20261021-submit-serial-8250-dma-config-errors-v1-v1-1-c067587d1ef2@gmail.com [2] https://lore.kernel.org/r/20261021-submit-serial-8250-dma-rx-accounting-v1-v1-1-c11795914ab4@gmail.com [3] https://lore.kernel.org/r/20261023-submit-serial-8250-dma-tx-length-v1-v2-1-c3106ef4d2df@gmail.com [4] https://lore.kernel.org/r/20261022-submit-serial-8250-tx-pm-shutdown-v1-v1-1-0e894afa3bb8@gmail.com Assisted-by: Codex:gpt-6-astra Signed-off-by: James Hilliard --- Changes in v4: - Retain flushed TX reservations through shutdown and failed resume. Release them after successful resume, or when allocating a new FIFO on reopen, so retirement cannot wake writers into a closing port. - Treat RX flush as complete once the channel is inactive, and clear the shutdown guard before startup configures the UART and tests interrupts. - Check completion after a failed pause so a transfer that finished before its callback acquired the port lock is delivered and retired normally. - Keep DesignWare's BUSY-safe divisor setter after fractional-divisor discovery, writing DLF and DLL/DLH only after confirming DLAB. - Link to v3: https://patch.msgid.link/20261023-submit-serial-8250-dma-cancel-v1-v3-0-d78f9e4c4932@gmail.com Changes in v3: - Defer write-ready wakeups while flushed TX storage is reserved, and serialize the flush wakeup with the reservation under the port lock. - Suppress ordinary TX starts during the reservation while preserving high-priority flow-control characters, which use separate storage. - Separate RX FIFO access from callback retirement, allowing PIO and the DesignWare empty-FIFO timeout workaround after a successful pause and termination while keeping the receive buffer reserved. - Use the existing IER shadow for requested enables and a shared register writer to keep receive interrupts masked throughout DMA error recovery, including termios, RS485, modem-status and overrun-backoff updates. - Preserve the timeout-enable bit across stop_rx(), exclude late shutdown interrupts from PIO, and avoid FIFO resets during RX DMA recovery. - Preserve the completion-path LSR read after stop_rx(), while gating DMA resubmission on the receive interrupt enable. - Pack the cancellation flags after moving all their accesses under the port lock, including the recovery worker's snapshot and initialization. - Apply the early-return, shared-helper and line-wrapping cleanups. - Link to v2: https://patch.msgid.link/20261022-submit-serial-8250-dma-cancel-v1-v2-0-088ea51e3891@gmail.com Changes in v2: - Add serial-core helpers to reserve flushed transmit storage until DMA retirement. Apply write backpressure during that interval and keep normal TX using the FIFO directly, replacing the private transmit buffer in v1. - Document the flush callback's reservation, writer backpressure and retirement requirements, including release before shutdown returns. - Split the OMAP completion refactor into a preparatory patch and move the RZ/N1 preparation-order and shutdown PM fixes to independent submissions, keeping four patches in this series. - Take runtime PM references around worker UART accesses, and leave normal RX retirement to release ownership without reading LSR or restarting DMA. - Synchronize the queued TX ranges before preparing the descriptor and return the mapping to CPU ownership before releasing the reservation. - Keep the TX transfer length separate from FIFO cancellation, so a failed termination can account completion without advancing the reset FIFO. - Exclude late RX flush work during shutdown, including Intel MID DMA timeout interrupts which are independent of UART_IER. - Accept DMA_IN_PROGRESS after successful pause, and recover from failed pause, termination or DMA_ERROR before handing the receiver to PIO. - Preserve stop_rx() and shutdown across recovery, and retain the DesignWare empty-FIFO timeout workaround when receiving through PIO. - Apply the requested guard spacing and container_of() formatting. - Link to v1: https://patch.msgid.link/20261021-submit-serial-8250-dma-cancel-v1-v1-0-efe2b89f2303@gmail.com --- James Hilliard (4): serial: 8250_omap: separate locked TX DMA completion processing serial: core: allow drivers to reserve flushed transmit storage serial: 8250: drain canceled TX DMA before reusing its buffer serial: 8250: retire canceled RX DMA before reusing the receive buffer drivers/tty/serial/8250/8250.h | 59 +++++++- drivers/tty/serial/8250/8250_core.c | 2 +- drivers/tty/serial/8250/8250_dma.c | 283 +++++++++++++++++++++++++++--------- drivers/tty/serial/8250/8250_dw.c | 34 +++-- drivers/tty/serial/8250/8250_mid.c | 6 +- drivers/tty/serial/8250/8250_omap.c | 38 +++-- drivers/tty/serial/8250/8250_port.c | 31 ++-- drivers/tty/serial/serial_core.c | 61 +++++++- include/linux/serial_core.h | 17 ++- 9 files changed, 414 insertions(+), 117 deletions(-) --- base-commit: 1184f87e2790e8af9be3116f608d2e86b4792d7d change-id: 20261021-submit-serial-8250-dma-cancel-v1-b208f84e89c1 prerequisite-patch-id: 3604bfaa3a1c214997de1f11162b81a4541af5ab prerequisite-patch-id: 79dd093ffb35e254e790dffb8887faf51b64f947 prerequisite-patch-id: 80a5061d84c055a64c760268febed179c687b99f prerequisite-patch-id: 7dbb404baf1f861982cf6a4b755d39cfec548223 prerequisite-patch-id: 40881d81a27b3a1aa45203d171214faaf2197768 Best regards, -- James Hilliard