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Fri, 23 Oct 2026 15:28:14 +0200 From: Gabriel Fernandez Date: Fri, 23 Oct 2026 15:28:12 +0200 Subject: [PATCH 7/7] clk: stm32mp25: add ck_ker_usb2phy1_stp clock X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20261023-ups_mp25_clk_update-v1-7-e906e7a38cb3@foss.st.com> References: <20261023-ups_mp25_clk_update-v1-0-e906e7a38cb3@foss.st.com> In-Reply-To: <20261023-ups_mp25_clk_update-v1-0-e906e7a38cb3@foss.st.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Gabriel Fernandez X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792762086; l=3648; i=gabriel.fernandez@foss.st.com; s=20261013; h=from:subject:message-id; bh=+AhRabnDo2MOuethLXNTFERrr/TJJpG8wVLAlbjfjgE=; b=MFVIwtMbmfybJMX9CArjD6g3D/z0fktX08cyPvC4b1zpnBqx5xuJ4ibZNG5YuskJkIl2jr1Sp HVuQbqKemxMD2o9Hovbjn7lcsMJBukc6gTwaQBXPPJt6mrKG8HUvZON X-Developer-Key: i=gabriel.fernandez@foss.st.com; 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Its rate is the one of ck_ker_usb2phy1. Set hse_ker_ck as the parent clock of ck_ker_usb2phy1_stp to ensure it remains active during the low power modes. Update the number of clocks of the provider to cover the new ID. Signed-off-by: Gabriel Fernandez --- drivers/clk/stm32/clk-stm32mp25.c | 41 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/clk/stm32/clk-stm32mp25.c b/drivers/clk/stm32/clk-stm32mp25.c index a6a1293370eb..649af99680f4 100644 --- a/drivers/clk/stm32/clk-stm32mp25.c +++ b/drivers/clk/stm32/clk-stm32mp25.c @@ -18,7 +18,7 @@ #include /* Number of clock identifiers of the binding, SCMI ones excluded: highest ID + 1 */ -#define STM32MP25_LAST_CLK (CK_SPI8_AM + 1) +#define STM32MP25_LAST_CLK (CK_KER_USB2PHY1STP + 1) /* Clock security definition */ #define SECF_NONE -1 @@ -356,6 +356,7 @@ enum enum_gate_cfg { GATE_USART6, GATE_USBH, GATE_USB2PHY1, + GATE_USB2PHY1STP, GATE_USB2PHY2, GATE_USB3DR, GATE_USB3PCIEPHY, @@ -506,6 +507,7 @@ static const struct stm32_gate_cfg stm32mp25_gates[GATE_NB] = { GATE_CFG(GATE_USART6, RCC_USART6CFGR, 1, 0), GATE_CFG(GATE_USBH, RCC_USBHCFGR, 1, 0), GATE_CFG(GATE_USB2PHY1, RCC_USB2PHY1CFGR, 1, 0), + GATE_CFG(GATE_USB2PHY1STP, RCC_USB2PHY1CFGR, 4, 0), GATE_CFG(GATE_USB2PHY2, RCC_USB2PHY2CFGR, 1, 0), GATE_CFG(GATE_USB3DR, RCC_USB3DRCFGR, 1, 0), GATE_CFG(GATE_USB3PCIEPHY, RCC_USB3PCIEPHYCFGR, 1, 0), @@ -1635,6 +1637,42 @@ static struct clk_stm32_composite ck_ker_usb2phy1 = { &clk_stm32_composite_ops, 0), }; +static int clk_stm32_usb2phy1_stp_enable(struct clk_hw *hw) +{ + return clk_stm32_gate_ops.enable(hw); +} + +static void clk_stm32_usb2phy1_stp_disable(struct clk_hw *hw) +{ + clk_stm32_gate_ops.disable(hw); +} + +static int clk_stm32_usb2phy1_stp_is_enabled(struct clk_hw *hw) +{ + return clk_stm32_gate_ops.is_enabled(hw); +} + +static unsigned long clk_stm32_usb2phy1_stp_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + /* The rate of ck_ker_usb2phy1_stp is the same as ck_ker_usb2phy1 */ + return clk_hw_get_rate(&ck_ker_usb2phy1.hw); +} + +static const struct clk_ops clk_stm32_usb2phy1_stp_ops = { + .enable = clk_stm32_usb2phy1_stp_enable, + .disable = clk_stm32_usb2phy1_stp_disable, + .is_enabled = clk_stm32_usb2phy1_stp_is_enabled, + .recalc_rate = clk_stm32_usb2phy1_stp_recalc_rate, +}; + +/* Parent clock of ck_ker_usb2phy1_stp is HSE_KER_ON to ensure it remains active during low power */ +static struct clk_stm32_gate ck_ker_usb2phy1_stp = { + .gate_id = GATE_USB2PHY1STP, + .hw.init = CLK_HW_INIT_INDEX("ck_ker_usb2phy1_stp", HSE_KER_ON, + &clk_stm32_usb2phy1_stp_ops, 0), +}; + /* USB2H */ static struct clk_stm32_gate ck_icn_m_usb2ehci = { .gate_id = GATE_USBH, @@ -1993,6 +2031,7 @@ static const struct clock_config stm32mp25_clock_cfg[] = { STM32_COMPOSITE_CFG(CK_KER_ADC12, ck_ker_adc12, SEC_RIFSC(58)), STM32_COMPOSITE_CFG(CK_KER_ADC3, ck_ker_adc3, SEC_RIFSC(59)), STM32_COMPOSITE_CFG(CK_KER_USB2PHY1, ck_ker_usb2phy1, SEC_RIFSC(63)), + STM32_GATE_CFG(CK_KER_USB2PHY1STP, ck_ker_usb2phy1_stp, SEC_RIFSC(63)), STM32_GATE_CFG(CK_KER_USB2PHY2, ck_ker_usb2phy2, SEC_RIFSC(63)), STM32_COMPOSITE_CFG(CK_KER_USB2PHY2EN, ck_ker_usb2phy2_en, SEC_RIFSC(63)), STM32_COMPOSITE_CFG(CK_KER_USB3PCIEPHY, ck_ker_usb3pciephy, SEC_RIFSC(67)), -- 2.43.0