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Fri, 23 Oct 2026 18:43:25 +0200 From: Gabriel Fernandez Subject: [PATCH v2 0/7] clk: stm32mp25: add Cortex-M0 D3 clocks, ETR/STM and USB2PHY1 STP Date: Fri, 23 Oct 2026 18:43:16 +0200 Message-ID: <20261023-ups_mp25_clk_update-v2-0-398d348ea8fd@foss.st.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAKSO22oC/22Nyw6CMBBFf4XM2pI+Iqgr/8MQUspUGoU2HSAa0 n+3krhzeU5yz92AMDokuBQbRFwdOT9lkIcCzKCnOzLXZwbJZSW4lGwJ1I5BHlvzfLRL6PWMrLZ Cc9UJU1kJeRkiWvfaq7cm8+Bo9vG9n6zia3899be3CsYZnnmFtVYn06mr9UQlzaXxIzQppQ+AC I5SuAAAAA== To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Gabriel Fernandez , Gwenael Treuveur X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792773804; l=3216; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: j2Ecz2dNuNTLw6pNW7gLa5LvPkSssWQ2ZTvN9hA8ermwI1XK/qf6LyjKvzft7TC2rynIIYqF++D+0lrAFTJKHgtLSx6Jk90i3eiIxy/SmWtDcQvnF0xtRI8NB4vXTMGMURLYdSRgDghfAW1Nq/jBdQzzURoXcllFxLMPuh2M1pID2JzV7XufFuP15FRaoJxbWzZPmA2AL2UXYUyiocmzE08rM5elVdfeS+LDWWdJAstx85yWUQeogEAneOoSqARjyjFe+7cDL7FHX5LGgjyTlI8RehoAhrXjp1gc5nBlN7EgVuy2Sq/X2OwspV8KwQUM1xhhDIvOwIdiFLSYp/akAlOUzzyoevEB+CZs9vKoHGu7tZ/GaZXfY9mfiwlRewtIbSDIxjj0Ga+VUo8GKOcyz5dDD6bBkcbV50dKIQyMajakngZ3DClHK7kHfWyrK5lV X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2026 16:43:26.1033 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1941abb4-89c8-4695-28ce-08df3124c284 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF00070CF3.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM7PR10MB3720 This series updates the STM32MP25 RCC bindings and clock driver: - Patch 1 makes the driver define the number of clocks of its provider (STM32MP25_LAST_CLK) instead of taking it from the binding header, and drops it from that header. That value is not part of the binding ABI and would have to change each time an ID is added. This is already how the STM32MP21 clock driver does it. No functional change. The driver and the header are changed by the same patch, as the macro has the same name in both. The driver patches 5 and 7 then update the number of clocks. - Patches 2-3 align the ETR and STM clocks with the reference manual: add their kernel clocks and rename the bus clocks and the RCC_STMCFGR register accordingly. The values of the renamed identifiers are unchanged and they have no user in the tree. - Patches 4-5 add the clocks to allocate the D3 peripherals to the Cortex-M0 (CPU3) and to enable their autonomous mode. The binding patch also adds the HSI, HSE and MSI kernel clocks as three new RCC input clocks. They are optional (minItems), so that the existing device trees remain valid. - Patches 6-7 add the ck_ker_usb2phy1_stp clock needed by USB host low power support, with the HSE kernel clock introduced by patch 5 as parent to keep it running in low power modes. The patches are kept in one series because the binding identifiers are allocated sequentially in the same header, and patch 7 uses the HSE kernel clock parent added by patch 5. Signed-off-by: Gabriel Fernandez --- Changes in v2: - Patch 7: drop the custom clock ops and the recalc_rate reading ck_ker_usb2phy1, and use clk_stm32_gate_ops directly. This fixes the missing .disable_unused (gate counter underflow in clk_disable_unused()) and the stale cached rate, as the rate is now derived by the CCF from the real parent. Both reported by the Sashiko AI review. - Patch 7: update the commit message accordingly. - Other patches are unchanged. - Link to v1: https://lore.kernel.org/r/20261023-ups_mp25_clk_update-v1-0-e906e7a38cb3@foss.st.com --- Gabriel Fernandez (6): clk: stm32mp25: define the number of clocks in the driver dt-bindings: stm32: add kernel clocks for ETR and STM clk: stm32mp25: update register with reference manual clk: stm32mp25: add clock for D3 peripherals allocation for Cortex-CM0 dt-bindings: stm32: add binding for usb2phy1stp clock on stm32mp25 clk: stm32mp25: add ck_ker_usb2phy1_stp clock Gwenael Treuveur (1): dt-bindings: stm32: add clock binding for Cortex-CM0 on stm32mp25 platform .../bindings/clock/st,stm32mp25-rcc.yaml | 9 +- drivers/clk/stm32/clk-stm32mp25.c | 187 +++++++++++++++++++++ drivers/clk/stm32/stm32mp25_rcc.h | 2 +- include/dt-bindings/clock/st,stm32mp25-rcc.h | 48 +++++- 4 files changed, 239 insertions(+), 7 deletions(-) --- base-commit: a90ee4305c4a5df72c11b31dacfdc76e00fcf78a change-id: 20261022-ups_mp25_clk_update-7f1a03b1c6f2 Best regards, -- Gabriel Fernandez