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Fri, 23 Oct 2026 18:43:27 +0200 From: Gabriel Fernandez Date: Fri, 23 Oct 2026 18:43:18 +0200 Subject: [PATCH v2 2/7] dt-bindings: stm32: add kernel clocks for ETR and STM X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-ID: <20261023-ups_mp25_clk_update-v2-2-398d348ea8fd@foss.st.com> References: <20261023-ups_mp25_clk_update-v2-0-398d348ea8fd@foss.st.com> In-Reply-To: <20261023-ups_mp25_clk_update-v2-0-398d348ea8fd@foss.st.com> To: Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue CC: , , , , , Gabriel Fernandez X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792773804; l=1944; i=gabriel.fernandez@foss.st.com; s=20261013; h=from:subject:message-id; bh=GSgOwjZDuhrIDIdVospjwtRBccbKbUndwKmf4/tHb7w=; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: oGNf5NdoOvwfHrp1MlZ41qsLMs/lAs0IZ62wDUsxO67M5O/HjAL7R8Y27ToJtSnET2mntCBKxonzNs4t535V8Jd3jWZjRB4xR4q0FBY69G5zlIUImm5Q/b4BzNSkyZg3hthCgdGYkGmF/SoiZ+61fAV/CtFR6mGEgCQOQx6TJSfOwm9r3ElZRQ4ygm/pelx34TLz24qrKW2IMmYlj1+bjUXp+EZBFFcciNBBQPnknbine8db3Leox2sz4H+1WsKw9vzO6LOZToT5Pb8KS1/hgJY8kUzhx5tLvs6geA0uz987tqYEmJk5t7kf+2j86pOkM9dzWJgxJfHIKhk90OEGWaMj4YcM/o01j+pfd3dZ2Y0+EPR4/r6kbRB1YfwtqId49c2lOv7XP3PbNRwMCQsGSuBEyhSeKSuTqiCU1+qBGniT0qoTA1QB+slHTYhqdz5L X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2026 16:43:27.8203 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8999b2bd-9632-49e1-4667-08df3124c38a X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF00070CF2.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR10MB3989 Add the kernel clocks of the ETR (CK_KER_ETR) and of the STM (CK_KER_STM) for STM32MP25, with the matching SCMI clocks (CK_SCMI_KER_ETR and CK_SCMI_KER_STM). These are the trace (ATB) clocks of the CoreSight Embedded Trace Router and System Trace Macrocell, while the bus clocks only provide register access (APB). Also rename the bus clocks according to the reference manual, without changing their values: CK_BUS_STM500 into CK_BUS_STM, CK_SCMI_STM500 into CK_SCMI_BUS_STM and CK_SCMI_ETR into CK_SCMI_BUS_ETR. Signed-off-by: Gabriel Fernandez --- include/dt-bindings/clock/st,stm32mp25-rcc.h | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/include/dt-bindings/clock/st,stm32mp25-rcc.h b/include/dt-bindings/clock/st,stm32mp25-rcc.h index 242f61205a9f..cef997508b56 100644 --- a/include/dt-bindings/clock/st,stm32mp25-rcc.h +++ b/include/dt-bindings/clock/st,stm32mp25-rcc.h @@ -109,7 +109,7 @@ /* LOW SPEED MCU CLOCK */ #define CK_ICN_LS_MCU 88 -#define CK_BUS_STM500 89 +#define CK_BUS_STM 89 #define CK_BUS_FMC 90 #define CK_BUS_GPU 91 #define CK_BUS_ETH1 92 @@ -363,6 +363,8 @@ #define CK_BUS_ETHSWACMCFG 341 #define CK_BUS_ETHSWACMMSG 342 #define HSE_DIV2_CK 343 +#define CK_KER_ETR 344 +#define CK_KER_STM 345 #define CK_SCMI_ICN_HS_MCU 0 #define CK_SCMI_ICN_SDMMC 1 @@ -450,7 +452,7 @@ #define CK_SCMI_TIMG2 83 #define CK_SCMI_BKPSRAM 84 #define CK_SCMI_BSEC 85 -#define CK_SCMI_ETR 87 +#define CK_SCMI_BUS_ETR 87 #define CK_SCMI_FMC 88 #define CK_SCMI_GPIOA 89 #define CK_SCMI_GPIOB 90 @@ -485,6 +487,8 @@ #define CK_SCMI_SYSDBG 119 #define CK_SCMI_SYSATB 120 #define CK_SCMI_TSDBG 121 -#define CK_SCMI_STM500 122 +#define CK_SCMI_BUS_STM 122 +#define CK_SCMI_KER_STM 123 +#define CK_SCMI_KER_ETR 124 #endif /* _DT_BINDINGS_STM32MP25_CLKS_H_ */ -- 2.43.0