From: "lianfeng.ouyang" <lianfeng.ouyang@starfivetech.com>
To: Olivia Mackall <olivia@selenic.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>
Cc: linux-crypto@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
Subject: [PATCH v10 5/6] hwrng: starfive - add JHB100 support
Date: Fri, 23 Oct 2026 10:12:47 +0800 [thread overview]
Message-ID: <20261023021248.3763-6-lianfeng.ouyang@starfivetech.com> (raw)
In-Reply-To: <20261023021248.3763-1-lianfeng.ouyang@starfivetech.com>
From: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
The JHB100 SoC has the same TRNG as the JH7110, but asserting its reset
while the clocks are still running causes reset-domain-crossing
glitches that can affect downstream IPs. It needs the clocks gated
before the reset is asserted, whereas the JH7110 keeps the original
reset-first order.
Describe the power-down ordering in per-compatible match data, select
it with device_get_match_data(), and add the "starfive,jhb100-trng"
compatible.
Signed-off-by: Lianfeng Ouyang <lianfeng.ouyang@starfivetech.com>
---
drivers/char/hw_random/jh7110-trng.c | 45 ++++++++++++++++++++++++++--
1 file changed, 42 insertions(+), 3 deletions(-)
diff --git a/drivers/char/hw_random/jh7110-trng.c b/drivers/char/hw_random/jh7110-trng.c
index 3bec7b53770e..1018a28f291d 100644
--- a/drivers/char/hw_random/jh7110-trng.c
+++ b/drivers/char/hw_random/jh7110-trng.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * TRNG driver for the StarFive JH7110 SoC
+ * TRNG driver for the StarFive JH7110/JHB100 SoCs
*
* Copyright (C) 2022 StarFive Technology Co.
*/
@@ -24,6 +24,7 @@
#include <linux/mutex.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
+#include <linux/property.h>
#include <linux/reset.h>
#include <linux/types.h>
#include <linux/workqueue.h>
@@ -101,6 +102,22 @@ enum starfive_trng_mode {
PRNG_256BIT,
};
+/*
+ * Power-down ordering of reset assertion vs. clock gating:
+ * SEQ_RST_FIRST - assert reset, then gate the clocks (JH7110).
+ * SEQ_CLK_FIRST - gate the clocks, then assert reset (JHB100). Asserting
+ * reset with the clocks running causes reset-domain-crossing
+ * glitches that can affect downstream IPs.
+ */
+enum seq_rst_clk {
+ SEQ_RST_FIRST,
+ SEQ_CLK_FIRST,
+};
+
+struct starfive_trng_data {
+ enum seq_rst_clk seq_rst_clk;
+};
+
struct starfive_trng {
struct device *dev;
void __iomem *base;
@@ -112,6 +129,7 @@ struct starfive_trng {
struct completion random_done;
struct completion reseed_done;
struct work_struct work;
+ const struct starfive_trng_data *data;
u32 mode;
u32 mission;
bool need_reseed;
@@ -209,7 +227,10 @@ static int starfive_trng_power_on(struct starfive_trng *trng)
static void starfive_trng_power_off(struct starfive_trng *trng, bool assert_rst)
{
- if (assert_rst && trng->rst_deassert) {
+ bool clk_first = trng->data->seq_rst_clk == SEQ_CLK_FIRST;
+ bool do_rst = assert_rst && trng->rst_deassert;
+
+ if (do_rst && !clk_first) {
reset_control_assert(trng->rst);
trng->rst_deassert = false;
}
@@ -219,6 +240,11 @@ static void starfive_trng_power_off(struct starfive_trng *trng, bool assert_rst)
clk_disable_unprepare(trng->hclk);
trng->clk_on = false;
}
+
+ if (do_rst && clk_first) {
+ reset_control_assert(trng->rst);
+ trng->rst_deassert = false;
+ }
}
static void starfive_trng_power_off_action(void *data)
@@ -507,7 +533,11 @@ static int starfive_trng_probe(struct platform_device *pdev)
return -ENOMEM;
platform_set_drvdata(pdev, trng);
+
trng->dev = dev;
+ trng->data = device_get_match_data(dev);
+ if (!trng->data)
+ return dev_err_probe(dev, -ENODEV, "No match data\n");
trng->base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(trng->base))
@@ -617,8 +647,17 @@ static int starfive_trng_resume(struct device *dev)
return 0;
}
+static const struct starfive_trng_data jh7110_data = {
+ .seq_rst_clk = SEQ_RST_FIRST,
+};
+
+static const struct starfive_trng_data jhb100_data = {
+ .seq_rst_clk = SEQ_CLK_FIRST,
+};
+
static const struct of_device_id trng_dt_ids[] = {
- { .compatible = "starfive,jh7110-trng" },
+ { .compatible = "starfive,jh7110-trng", .data = &jh7110_data },
+ { .compatible = "starfive,jhb100-trng", .data = &jhb100_data },
{ }
};
MODULE_DEVICE_TABLE(of, trng_dt_ids);
--
2.43.0
next prev parent reply other threads:[~2026-10-23 2:13 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-23 2:12 [PATCH v10 0/6] hwrng: starfive - fixes and " lianfeng.ouyang
2026-10-23 2:12 ` [PATCH v10 1/6] dt-bindings: rng: starfive,jh7110-trng: add jhb100, drop jh8100 lianfeng.ouyang
2026-10-23 2:12 ` [PATCH v10 2/6] hwrng: starfive - fix runtime PM and power teardown handling lianfeng.ouyang
2026-10-23 2:12 ` [PATCH v10 3/6] hwrng: starfive - move the SEU reseed out of the interrupt handler lianfeng.ouyang
2026-10-23 2:12 ` [PATCH v10 4/6] hwrng: starfive - tidy up includes and drop unused code lianfeng.ouyang
2026-10-23 2:12 ` lianfeng.ouyang [this message]
2026-10-23 2:12 ` [PATCH v10 6/6] MAINTAINERS: update the StarFive TRNG driver maintainer lianfeng.ouyang
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