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Fri, 23 Oct 2026 00:53:01 -0700 (PDT) Received: from server.lan ([168.138.199.194]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-195eae0e830sm4122132c88.10.2026.10.23.00.52.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 00:53:01 -0700 (PDT) From: Coia Prant To: Andrew Lunn , Heiner Kallweit , Russell King , "David S . Miller" , Jakub Kicinski , Paolo Abeni Cc: Eric Dumazet , Heiko Stuebner , Coia Prant , netdev@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net v2 1/4] net: pcs: xpcs-plat: fix runtime PM initialization Date: Fri, 23 Oct 2026 15:52:12 +0800 Message-ID: <20261023075214.1793922-3-coiaprant@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20261023075214.1793922-2-coiaprant@gmail.com> References: <20261023075214.1793922-2-coiaprant@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The driver calls pm_runtime_set_active() before runtime PM is enabled and before the CSR clock is prepared and enabled. If the device is later suspended (e.g. during unbind), the runtime suspend callback tries to disable a clock that was never enabled, producing: clk_csr already disabled clk_csr already unprepared Set the initial runtime PM status to suspended instead, and register a devm action that force-suspends the device on teardown. Without that action the CSR clock would stay enabled if the driver is removed while runtime-active, since nothing triggers a runtime suspend on unbind. pm_runtime_force_suspend() is not checked because the runtime suspend callback cannot fail. The clock is enabled on the first runtime resume (e.g. during MDIO access). No upstream platform currently enables this driver with a real CSR clock dependency, so the issue is not reachable in mainline today. It was found while using this driver as a reference for the Rockchip XPCS glue driver. Signed-off-by: Coia Prant --- drivers/net/pcs/pcs-xpcs-plat.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/drivers/net/pcs/pcs-xpcs-plat.c b/drivers/net/pcs/pcs-xpcs-plat.c index e669a7b248ac..11c4239bfd74 100644 --- a/drivers/net/pcs/pcs-xpcs-plat.c +++ b/drivers/net/pcs/pcs-xpcs-plat.c @@ -275,6 +275,14 @@ static int xpcs_plat_init_res(struct dw_xpcs_plat *pxpcs) return 0; } +static void xpcs_plat_exit_clk(void *data) +{ + struct dw_xpcs_plat *pxpcs = data; + struct device *dev = &pxpcs->pdev->dev; + + pm_runtime_force_suspend(dev); +} + static int xpcs_plat_init_clk(struct dw_xpcs_plat *pxpcs) { struct device *dev = &pxpcs->pdev->dev; @@ -285,10 +293,12 @@ static int xpcs_plat_init_clk(struct dw_xpcs_plat *pxpcs) return dev_err_probe(dev, PTR_ERR(pxpcs->cclk), "Failed to get CSR clock\n"); - pm_runtime_set_active(dev); - ret = devm_pm_runtime_enable(dev); + pm_runtime_set_suspended(dev); + pm_runtime_enable(dev); + + ret = devm_add_action_or_reset(dev, xpcs_plat_exit_clk, pxpcs); if (ret) { - dev_err(dev, "Failed to enable runtime-PM\n"); + dev_err(dev, "Failed to register devm for xpcs_plat_exit_clk: %d\n", ret); return ret; } -- 2.47.3