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Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by SG1PEPF000082E6.mail.protection.outlook.com (10.167.240.5) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.15 via Frontend Transport; Fri, 23 Oct 2026 09:30:46 +0000 Received: from ubuntu (unknown [172.20.64.99]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id B5DC54102B40; Fri, 23 Oct 2026 17:30:45 +0800 (CST) From: Jelly Jia To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, robin.murphy@arm.com, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org, cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com, linux-clk@vger.kernel.org, joakim.zhang@cixtech.com Subject: [PATCH v1 0/5] soc: cix: Add the Sky1 AUDSS DMA-350 interrupt path Date: Fri, 23 Oct 2026 17:30:40 +0800 Message-ID: <20261023093045.3248630-1-Jelly.Jia@cixtech.com> X-Mailer: git-send-email 2.55.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SG1PEPF000082E6:EE_|KL1PR06MB7317:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 66f3c66d-97d8-4b96-dd52-08df30e851b5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|7416014|376014|23010399003|1800799024|6133799003|3023799007|18002099003|10067099003|261022105027099003|260925021911599003|260925021311599003|260925022911599003|261021121427099003|261009223027099003|5023799004|261021123027099003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: JYfUByImXIrTlHZDK+gmchZN0NRxhPNJ/+V6QeWOE1BqE/o0retFq0hbOqBUdjQxN3i83IuloVJ9HtGMevGshKrU+ZRAWDLkcrw+e0C4GsC+gZYLQxE0DWd/Oaq+oahcew4h7XJARq+apv/sRZU2VlRS+IEkxpw857VDKSmK+fy+oie9CblQQmfynOwstHrzjGrWvc970v0Bc3Zm2BfaS9JSjm7DCf6BcrNchPuE9o8KYxJozGqx+Vs96U2qlg/Jt/aS9rHX4BuPagd66PSkraeKRzhSNFaH03Ikb1ns+js23902SoZ3T48CyJF0mDo6iDCF4R/i/NwJDVn9j6LlMxrdLACgLKdrkSw+KCjrNJaHCV6AwIwBurcnq7rVw/rZKvwIoZhGaLbbLFkkgx18nHPPxG/SN+1GRjWpmepgusldfcTFeB4Smn9D+FdZ4H/t X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Oct 2026 09:30:46.6610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 66f3c66d-97d8-4b96-dd52-08df30e851b5 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: SG1PEPF000082E6.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: KL1PR06MB7317 Hello, This series adds the CIX Sky1 AUDSS DMA-350 and its interrupt path through the audio subsystem CRU. The DMA, CRU and DT changes are posted together because the controller depends on the CRU interrupt gates, while dma-channel-mask describes which channels Linux may use. Keeping them together allows the complete interrupt path to be reviewed. If separate submissions are preferred, they can be split in the next revision. No audio client drivers are added here. It depends on the companion v4 series, "dmaengine: arm-dma350: Add slave support and Sky1 integration", for slave/cyclic transfers and optional clock and reset support. Apply that series first. The CRU gates the AP interrupt path for each of the eight DMA channels and combines enabled inputs onto GIC SPI 230. Channels may be reserved for firmware or the DSP; dma-channel-mask limits those available to Linux. The AP gate bits control interrupt delivery, not channel ownership, and this series does not implement runtime AP/DSP ownership transfer. Conor suggested interrupt-map when the routing was described as being configured by firmware. This revision instead manages each AP gate via irq_mask and irq_unmask. A static interrupt-map alone would translate child specifiers to the shared GIC SPI but would not provide that gate control. Model the CRU as an irqchip so the register owner manages the gates, without CRU register accesses in the DMA driver. Feedback on this choice of irqchip rather than a static interrupt-map is welcome. The gate register exposes no per-channel pending status. The chained handler dispatches every enabled child, and each DMA channel handler checks its own status. The children use the untracked flow handler so inactive channels returning IRQ_NONE do not accumulate spurious-IRQ counts. The AUDSS DT describes a 1 MiB peripheral window and a 512 MiB DRAM window with dma-ranges. The prerequisite series allocates linked commands from a coherent DMA pool, so successfully allocated commands are reachable through the controller's DMA address windows. Signed-off-by: Jelly Jia Jelly Jia (5): dt-bindings: soc: cix: Describe the Sky1 AUDSS DMA IRQ controller clk: cix: Handle Sky1 AUDSS DMA interrupt gates as an irqchip dt-bindings: dma: arm,dma-350: Document dma-channel-mask dmaengine: arm-dma350: Honour dma-channel-mask arm64: dts: cix: Add the Sky1 AUDSS DMA-350 integration .../devicetree/bindings/dma/arm,dma-350.yaml | 3 + .../bindings/soc/cix/cix,sky1-audss-cru.yaml | 44 ++++++- arch/arm64/boot/dts/cix/sky1.dtsi | 26 +++- drivers/clk/cix/clk-sky1-audss.c | 122 ++++++++++++++++++ drivers/dma/arm-dma350.c | 20 ++- 5 files changed, 211 insertions(+), 4 deletions(-) base-commit: cee9395acd8043be0644b25c34bfa86623f2b935 prerequisite-patch-id: aad1bc3c30a4825048143a3e0395e696201548e9 prerequisite-patch-id: ac69e4704329a579e556880cffc061b2743e30af prerequisite-patch-id: ddc9ee115f12a7d2ee7ceff7e0485e7166581756 prerequisite-patch-id: 3d5fb2f7a5b2da42cb013d1c2e0a6e5eac5ffd6a prerequisite-patch-id: 0e54074dcfd104480233bb076d2424e6ba1bd25e -- 2.54.0