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[93.34.92.187]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-48e380310b3sm5076321f8f.22.2026.10.23.04.56.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 04:56:59 -0700 (PDT) From: Christian Marangi To: Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Ripard , linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Christian Marangi Subject: [PATCH 1/2] dt-bindings: gpio: fairchild,74hc595: add support for nxp,74lv164 Date: Fri, 23 Oct 2026 13:56:48 +0200 Message-ID: <20261023115652.700765-1-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Document support for nxp,74lv164 as a variant of the currently supported 8-bit shift register with the only difference of not having an Output Enable pin and a simulated Chip Select pin. These basic 8-bit shift register chips directly change the outputs as bits are shifted in. Particularly used to handle multiple LED for basic state feedback. Signed-off-by: Christian Marangi --- .../bindings/gpio/fairchild,74hc595.yaml | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index 451538df63f7..0d5596af0ced 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -7,9 +7,9 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Generic 8-bit shift register description: | - NOTE: These chips nominally don't have a chip select pin. They do however - have a rising-edge triggered latch clock (or storage register clock) pin, - which behaves like an active-low chip select. + NOTE: These chips nominally don't have a chip select pin. 59x chip family + do however have a rising-edge triggered latch clock (or storage register + clock) pin, which behaves like an active-low chip select. After the bits are shifted into the shift register, CS# is driven high, which the 74HC595 sees as a rising edge on the latch clock that results in a @@ -22,6 +22,9 @@ description: | ___ ________ chip select# |___________________| + Other chip family (namely 164) directly change the outputs as bits are shifted + in. + maintainers: - Maxime Ripard @@ -29,6 +32,7 @@ properties: compatible: enum: - fairchild,74hc595 + - nxp,74lv164 - nxp,74lvc594 reg: @@ -76,6 +80,14 @@ required: allOf: - $ref: /schemas/spi/spi-peripheral-props.yaml# + - if: + properties: + compatible: + contains: + const: nxp,74lv164 + then: + properties: + enable-gpios: false unevaluatedProperties: false -- 2.55.0