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Sat, 24 Oct 2026 03:31:09 -0700 (PDT) Received: from hu-akhilpo-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-19894d5a10csm6009441c88.1.2026.10.24.03.31.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 03:31:08 -0700 (PDT) From: Akhil P Oommen Date: Sat, 24 Oct 2026 16:00:13 +0530 Subject: [PATCH 7/8] drm/msm/a6xx: Request CLX enable from secure world X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261024-assorted-fixes-oct-v1-7-2977f974ddb7@oss.qualcomm.com> References: <20261024-assorted-fixes-oct-v1-0-2977f974ddb7@oss.qualcomm.com> In-Reply-To: <20261024-assorted-fixes-oct-v1-0-2977f974ddb7@oss.qualcomm.com> To: Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , Jordan Crouse , Neil Armstrong , =?utf-8?q?Christian_K=C3=B6nig?= , Luben Tuikov , Antonino Maniscalco Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Akhil P Oommen X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1792837816; l=1301; i=akhilpo@oss.qualcomm.com; s=20240726; h=from:subject:message-id; bh=f62WUqPk8JPeePU+Bm0XkICywuM1HT6Ax9xW96mzE4s=; b=WscAtm2o3l9CuzM+yZyAhNMO4ROOr682SdqdY3B1OcYV8NsoR7qljmwjsKmFf4kVDrTUY7a01 LA5ob8zUl7YBrSjAk9PR2k85RLWiddD/HL3Vmz1um9xkdx7xUQEMeTl X-Developer-Key: i=akhilpo@oss.qualcomm.com; a=ed25519; pk=lmVtttSHmAUYFnJsQHX80IIRmYmXA4+CzpGcWOOsfKA= X-Authority-Analysis: v=2.4 cv=Z8Z5j3RA c=1 sm=1 tr=0 ts=6adc88ee cx=c_pps a=kVLUcbK0zfr7ocalXnG1qA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=p4fv3_zKGVfQUpdSR-gA:9 a=QEXdDO2ut3YA:10 a=vr4QvYf-bLy2KjpDp97w:22 X-Proofpoint-ORIG-GUID: sw7K2N5c37LmPrSDb4P5FrKvR8dxZZgm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI0MDA0MSBTYWx0ZWRfXzbzbJZU5zqDQ v7emUcIIeUn6W6z1OHi1TfGOGX41oCs4y5lfKKNi/ATDlmXxuE/QqvlkYKxcvRlzUr1Fw+iV80t XGg0hoqpXRUTvU0d6xd+Omc/86Iq1wXQzws3y5c8aC3qxxWktcFeevr/YVmDgmI1/WL1uY6hYXh TVKS7wGMAQYFwhlfgX+72YPSI0m3EBbhdnYQxWCe1GvhV53gSgedd93nkcE+j/ugMkuFKq3fhCN A8/bA732mtMMPG8V+JlJCSGVNLqmNyDvhCEe0eFIKQN/kmcztO3OPGYXWAS7Yd7bd//1JwwCKjn KCN88RwUTfEwqiXPVICqP7sFHWOdHJdaJwXvZX1lFcbc/cactatHmdnxgM+lNgyEjP+tb4EWMmE cjzsiWL/fHL+tR7y6WcV8jHm1uS2/Ucx1IpjaZiINrWRVy4JiMQDJ5TIxKiuS+lzmx3j+5jlbn+ jS7eUqFr5UoBFQZnedQ== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI0MDA0MSBTYWx0ZWRfX6OWwU/+dfXEh bfvBXs7CXrUrHDtm+p9kSL8+OqVU29z2EpHdNtd8qPbYePnZ6QQ1QbVbeelEKyIVAJAGsjKTGKU qpm40M7d9UNeMIvsZkpZ8z2HjJ2SLFs= X-Proofpoint-GUID: sw7K2N5c37LmPrSDb4P5FrKvR8dxZZgm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-24_01,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610240041 The CLX (Current Limit Extension) feature also requires the secure world to enable it via the GPU init regs SCM call. Without the QCOM_SCM_GPU_CLX_EN_REQ flag, the CLX tables sent to the GMU over HFI are not effective. Set QCOM_SCM_GPU_CLX_EN_REQ in the SCM request on GPUs that have a CLX table in their catalog entry. Fixes: 967e62fbeecc ("drm/msm/a6xx: Add HFI support for CLX feature") Signed-off-by: Akhil P Oommen --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 991db3c9cd96..a1561ca41a5b 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1247,8 +1247,12 @@ static int a6xx_gmu_secure_init(struct a6xx_gpu *a6xx_gpu) goto done; } - ret = qcom_scm_gpu_init_regs(QCOM_SCM_GPU_ALWAYS_EN_REQ | - QCOM_SCM_GPU_TSENSE_EN_REQ); + u32 gpu_req = QCOM_SCM_GPU_ALWAYS_EN_REQ | QCOM_SCM_GPU_TSENSE_EN_REQ; + + if (adreno_gpu->info->a6xx->clx_tbl) + gpu_req |= QCOM_SCM_GPU_CLX_EN_REQ; + + ret = qcom_scm_gpu_init_regs(gpu_req); if (ret) { dev_warn_once(gpu->dev->dev, "SCM call failed\n"); -- 2.55.0