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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-369e8ec50bcsm24133054eec.23.2026.10.24.20.17.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 20:17:26 -0700 (PDT) From: Hangxiang Ma Date: Sat, 24 Oct 2026 20:17:21 -0700 Subject: [PATCH v22 02/14] phy: qcom-mipi-csi2: Parametrise the common status register offset X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261024-kaanapali-camss-v22-2-7da3ea49c8a1@oss.qualcomm.com> References: <20261024-kaanapali-camss-v22-0-7da3ea49c8a1@oss.qualcomm.com> In-Reply-To: <20261024-kaanapali-camss-v22-0-7da3ea49c8a1@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma X-Mailer: b4 0.16.1-dev-17221 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI1MDAxMiBTYWx0ZWRfXydNqJaTfD5iM jUFBpev1pJvjXtdwKoYLlz6+UOKzEPcPscpBZ+d4l7jC7jaz2fT2ZYPuQwPhA7jk7oOqFWtPaY4 fNvHDRKLGGSVj5MHYEE2aoHo1G2A7xI= X-Proofpoint-GUID: fdluN8W6cuKT6FtOy9pUfZVjYLfk-SlP X-Authority-Analysis: v=2.4 cv=JvhkP84C c=1 sm=1 tr=0 ts=6add74c8 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=P6Xs4Y00w1yHQXPR5eoA:9 a=QEXdDO2ut3YA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI1MDAxMiBTYWx0ZWRfXylnx8K4oYJ9h QtGB89mh1GmT6UStTn0uXelZPUzOQeUuGBuqFCUm+MKbJDlNXQkvsYKW/mdKOx2Gs5YbrrACafn vBp1pLIFQLsBsjW2qgOFz1tv5xe5DgLMBxXgr959baTeK5c92S4g1tzNVnTqj8Tdy9H/3lX5uCO 7BZbxIdyJEcl8bcoribH+ppFm9mfbOZUJpvqPYQL64NN6cTiJlPoDO0ghJCb/kvLs8mULPLCY4h BmqnYfOUqasZWKyGk5oKu/4LMkYTpfFOq/4ShY/ybpGXHKaK3xTgaHWgJAgyskV2WreRyCKp3ec t3dCKdLVCVRZO/zA6sMurbre7+HHPc1crJ4+jVgdSYoyM1Xd6si340uF8hUy8D3rPuzJQRvn4fC Pn6ya5GhcDmSNZA9CmwBdSBhAjnAeMlozS+g0VvoTwYh23M8DDWIAx1y7uJJ1qX004mJ4Xc5a0j qwqwq7zpXLS7xLG25+A== X-Proofpoint-ORIG-GUID: fdluN8W6cuKT6FtOy9pUfZVjYLfk-SlP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-25_01,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 impostorscore=0 adultscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610250012 The CSI2 PHY common status registers are not at a fixed offset from the common register block across SoCs: x1e80100 uses 0xb0 while other 3PH v2.4.0 parts differ. Replace the hard-coded 0xb0 in CSIPHY_3PH_CMN_CSI_COMMON_STATUSn() with a per-SoC common_status_offset field in struct mipi_csi2phy_device_regs, initialising x1e80100 to 0xb0 so behaviour is unchanged. This is a no-functional-change preparation for describing other SoC offsets. Reviewed-by: Bryan O'Donoghue Signed-off-by: Hangxiang Ma --- drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 16 +++++++++++----- drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 1 + 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c index 966d79c98f9b..8cd331cfb4b3 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c @@ -19,7 +19,8 @@ #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_COMMON_PWRDN_B BIT(0) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL6_SHOW_REV_ID BIT(1) #define CSIPHY_3PH_CMN_CSI_COMMON_CTRL10_IRQ_CLEAR_CMD BIT(0) -#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, n) ((offset) + 0xb0 + 0x4 * (n)) +#define CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(offset, common_status_offset, n) \ + ((offset) + (common_status_offset) + 0x4 * (n)) #define CSIPHY_2PH_LN_CSI_2PHASE_CTRL9n(n) ((0x200 * (n)) + 0x24) @@ -176,19 +177,23 @@ static void phy_qcom_mipi_csi2_hw_version_read(struct mipi_csi2phy_device *csi2p CSIPHY_3PH_CMN_CSI_COMMON_CTRLn(regs->common_regs_offset, 6)); tmp = readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 12)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 12)); csi2phy->hw_version = tmp; tmp = readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 13)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 13)); csi2phy->hw_version |= (tmp << 8) & 0xFF00; tmp = readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 14)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 14)); csi2phy->hw_version |= (tmp << 16) & 0xFF0000; tmp = readl_relaxed(csi2phy->base + - CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, 15)); + CSIPHY_3PH_CMN_CSI_COMMON_STATUSn(regs->common_regs_offset, + regs->common_status_offset, 15)); csi2phy->hw_version |= (tmp << 24) & 0xFF000000; dev_dbg_once(csi2phy->dev, "CSIPHY 3PH HW Version = 0x%08x\n", csi2phy->hw_version); @@ -375,6 +380,7 @@ const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = { .init_seq = lane_regs_x1e80100, .lane_array_size = ARRAY_SIZE(lane_regs_x1e80100), .common_regs_offset = 0x1000, + .common_status_offset = 0xb0, }, .supply_names = (const char **)x1e_supplies, .num_supplies = ARRAY_SIZE(x1e_supplies), diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h index 7e55ae007370..d6366f809e51 100644 --- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h +++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h @@ -51,6 +51,7 @@ struct mipi_csi2phy_device_regs { const struct mipi_csi2phy_lane_regs *init_seq; const int lane_array_size; const u32 common_regs_offset; + const u32 common_status_offset; }; struct mipi_csi2_genpd { -- 2.34.1