From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=205.220.168.131 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1792898257; b=LJVpnTRJJh99QcqKIA8kr9yfxgnvZBOD4EPRCAmF7JYNOmspPmKlb5xqfsT9WaGj9hRK qMt4TDZbc/kkQ4f3DIR6xJm/+jhb935jUATjp2Seun/7SBraGX7L2dN8rikyU7wNIIC6q fblCOLcklC6ZvbFo9iKeETwNO0gj0bK3WUwOQQP/pQEDLmgnl8DUsbpvMQ8PftKsWsZU1 DczRdf+Zl/dhojcdOj2A8KfeT0+wUvJJoVcNwBIMpHT96+VJ0RCU+8KDqAFBNpCDaw3uf 5wrFS8uneupu5h/dfjxZzIqfi8yvyWLpHMUEf6c2K37tTiugTz+TjNTrDtS5RApe/LQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1792898257; h=DMARC-Filter:Received:DKIM-Signature:Received:Received: DKIM-Signature:X-Google-DKIM-Signature:X-Forwarded-Encrypted: X-Gm-Message-State:X-Gm-Gg:X-Received:X-Received:Received:From:Date: Subject:MIME-Version:Content-Type:Content-Transfer-Encoding: Message-Id:References:In-Reply-To:To:Cc:X-Mailer:X-Proofpoint-GUID: X-Proofpoint-Spam-Details-Enc:X-Authority-Analysis: X-Proofpoint-ORIG-GUID:X-Proofpoint-Spam-Info: X-Proofpoint-Virus-Version:X-Proofpoint-Spam-Details; bh=C2QGMQPpgntfOlymvqKpZeefMdcuixcvSXz4fPhN0qc=; b=pCe/th2doN4T+X+OQw7XMWIsGPtb313DNw2asZOLHKF/UTWxs+fFdOiNJUFW0Xqxh5eX YnE14FsKXIMyn5Z7ImBit/PhHW/lHGiajjZPMA3Nd9NgBP9CMa1asFSgmG72RC+rXNoSe Og7bSGClqFQpqddJJBf9kuQzIOj3IUuIxoT2xl30SiFuc7yHpmNMv1k7kNKwWOyLhR70Y gJFrXZfbxHHUpOsZgEcXrQ9Mr5uDBw/3MrQgD2FCSXVJOiyeWEtd9PAg7GDideXPyzOba CMzJN6YDmzTc8QvotttKbpy/dm9zZKbSOC387SQ6+EEcfIUjjLikT1bFLJWmXfuTl5g== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=nEH6rxPx; dkim=pass header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.a=rsa-sha256 header.s=google header.b=MDUq1jRE; arc=none smtp.remote-ip=205.220.168.131 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D845560A5BE5 for ; Sun, 25 Oct 2026 03:17:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org D845560A5BE5 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256 header.s=qcppdkim1 header.b=nEH6rxPx; dkim=pass (2048-bit key, unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.a=rsa-sha256 header.s=google header.b=MDUq1jRE Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 69P165be2207233 for ; Sun, 25 Oct 2026 03:17:35 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= C2QGMQPpgntfOlymvqKpZeefMdcuixcvSXz4fPhN0qc=; b=nEH6rxPxn14huNDb Me50EO7sQANz1HebAUwycd42caJTJtAaT2uOqOvTAXpDXFJ8kaw2v1pgsXp4GY7T 2E9dUdOAVU8dQnyEMtwIAp7D9j8YGU4luHYaHJwFSVcV045q2lr1fYSo2KkieBqi 40MKW190+sXzPcxFDoTSxLWgZ7uRuzJobwNKgb/YxaOI4H3/16pCg/8QAEx6WqDC ArngQPK0ZJA+jr0Fe+1eyYwCHEAuMhVIIRcoOHVWD7Hgil457bR0lv+7RZW94Rbf bK31DsxzgFzc17eLESQ0DiagyRfca6nf7lVANny7ITjHrQ62SEf9kUZzNdfgkLUP 78rKXA== Received: from mail-dy1-f197.google.com (mail-dy1-f197.google.com [74.125.82.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4hgny9t5gg-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Sun, 25 Oct 2026 03:17:35 +0000 (GMT) Received: by mail-dy1-f197.google.com with SMTP id 5a478bee46e88-36998507c13so732266eec.0 for ; Sat, 24 Oct 2026 20:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1792898254; x=1793503054; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=C2QGMQPpgntfOlymvqKpZeefMdcuixcvSXz4fPhN0qc=; b=MDUq1jREG9yE49aBCBO27Z0aSL+tcTLw7JiiHmIznDigqKECLfXIjudN9sQ8XCSbC7 dILn52JBAt0wMnAp9pwoe6l/xgnJ6WNR5NcUAfLyxiDDEIilUmbAvg7P/qG8b3i5IYCU XAsFwNychCUHtW/GvAj4Hr/GT6dRgCoOQpeY6QkQwLc4OCeZoIT8WEdoAzOehyg1MUer sx3CXCdu0cJzEm39TStH2zqhYkHtJfmrjOleaGEw+afAYhQSXGkDHIkoXmZiGem09+lp AIIiTVjDUyRsmTk9ICCbOpfqWsV37iNXtZuiAiZzrTYqZOnbEJWKd6ZSadW9S9ZylA9U j4Iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1792898254; x=1793503054; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :content-type:mime-version:subject:date:from:x-gm-gg :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to :content-type; bh=C2QGMQPpgntfOlymvqKpZeefMdcuixcvSXz4fPhN0qc=; b=s1NoVIWVuL8ICHwLpCB9IGvjDxrIsuS+TLuc11FcziwpMLjdcislWn56aSgbl1OP1J T7kgKfEN9DLHLbrFUYzjBuA4V+ACRKXnFoKNsrY/PoYKLzHe7NwCTOw3kAcOXIUo9FQy CiS8LyMVvexcPaUbctW/s3ENio9FhMJBkXanZJFwpoCJeutTzGoV3F4bQtwhtrVYZbYo B5SJJldDz3K7PJpXN8hoY3IHn1o56XBwXaZm4Gc2YJvhUtPR78sbar8kCzNr+tTqGOoo gufvk7nk8RLjGYDBomqv6iHawhxqv1gy/22o2DoL2ouhFLH7Fks6vQH95a3bYXnyuN9C iBWw== X-Forwarded-Encrypted: i=1; AKwUvBxIic8o4mzX6KtkhNIdNf6RVJyReoPYnF2xp1Kj99jNwyXXxTszMxVY2v5dXT9csRWav+5C8dfpaBGDG54=@vger.kernel.org X-Gm-Message-State: AFq9FYJjZPUCTZs+otLl4aGsWs827V9F7OpalSUP8vSH142JCdWkpiwG hUpZAJbZoJxuu+pEIbPfbe7AEr/Xuxe4PfhPZb0UhoLIHjLUAGbVVR+fXlm///OyFDibAPoHwy5 WnvgP9xkmzx1qqI84YOBAAYqwsl1CFvmIr8KiegzbX5jeWpCpvtTq47Kp05BQk+pDjtI= X-Gm-Gg: AYBFou0+5IL5CbjU8CnCyQv/r2y1Jei7a0AfsUi2OXM8AgN2lj9e5UlF62FX3hzh+AI NkWC589XhHra+mpQg7olZn5dF2Rr0yXRS8npiteESYWtx5YL7otfDeuZCJ9P9xOQ2G8lHz1eADd NTkhUs5UYC0cBd/I561Fy1jEx+ZV14z/omvXh1gxe3LPL5FLPQ+Ax7k3XHcLA8ceA4Zok99nS6T inqiUMuEf4r99QUaNC/oIno74Pi+vwAm2Y88pz/xTTH0UZ52to/kJlFGH+Q9ggHbFIb6Z3M+cqo xFzogA5zfYz6YuwofABqfdzY2fYbz3Eo2oRyWBkfLjgQM/PHCctvjZpdaoOzrslaMZNWGUkjigz Rv9a3ed8Oq5HR3JM733eJAhtH5KPOeyMq6xj4PVFPRrHXv3qX3WOojNGVHJaC/iKxBm4EHwjAe7 AhcXn1IQj9HA== X-Received: by 2002:a05:693c:2802:b0:367:41d7:9deb with SMTP id 5a478bee46e88-369e84bd8bcmr4770614eec.33.1792898254003; Sat, 24 Oct 2026 20:17:34 -0700 (PDT) X-Received: by 2002:a05:693c:2802:b0:367:41d7:9deb with SMTP id 5a478bee46e88-369e84bd8bcmr4770572eec.33.1792898253325; Sat, 24 Oct 2026 20:17:33 -0700 (PDT) Received: from hu-hangxian-lv.qualcomm.com (Global_NAT1.qualcomm.com. [129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-369e8ec50bcsm24133054eec.23.2026.10.24.20.17.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 20:17:32 -0700 (PDT) From: Hangxiang Ma Date: Sat, 24 Oct 2026 20:17:27 -0700 Subject: [PATCH v22 08/14] media: qcom: camss: csid: Add support for CSID 1080 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20261024-kaanapali-camss-v22-8-7da3ea49c8a1@oss.qualcomm.com> References: <20261024-kaanapali-camss-v22-0-7da3ea49c8a1@oss.qualcomm.com> In-Reply-To: <20261024-kaanapali-camss-v22-0-7da3ea49c8a1@oss.qualcomm.com> To: Bryan O'Donoghue , Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bryan O'Donoghue , Vladimir Zapolskiy , Loic Poulain , Mauro Carvalho Chehab , Bjorn Andersson , Konrad Dybcio , Abel Vesa Cc: linux-phy@lists.infradead.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, jeyaprakash.soundrapandian@oss.qualcomm.com, Vijay Kumar Tumati , Hangxiang Ma , Atiya Kailany X-Mailer: b4 0.16.1-dev-17221 X-Proofpoint-GUID: ua4MSSc6qQtY9UXMh_02TIkHHgwIC-vZ X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI1MDAxMiBTYWx0ZWRfX715+iFuBfj5F dWPEAepAFgAgUw9H/HIdPwxYoJQikg5pu++hOEcd7Gf1ns4IbgF2RfmwIrqvxcwcT8hVChWsy8E ytxbJhYqLkhtgbQSwUFrUfSIsW5wzgx9YL/2Gb0b9yRzwbkNWFrjl4O8FSFGp2VFQem/gQTNKqG r3T0KH6xjUDenj1Ax6ZGyy7OgOPRL2jX3azuo0CncjxuFGlhgtRVTpx3WkORapsfoF3pWlsV9YA 1AoOipH3mhFS0rp7hde4Hd0nGgb4PoE5qYhU3oXzTT+xK+hefb2HLyb1GeGMVlIwmnQyzhT+QGU +0pWRfbi/sPN2TU7xcCRrFa2aP5giCgWJgpCN++Kcu+zXYBQdGRkzc51po0DCXL+Xh3AL0YRFsx aBvPDurhND2W35riLe64WFjxk+I0CnkcAbymjH44jimIZI6y6Yjji8yyBr6wSGif5xvMlEmwpA1 wi1b/hU02mJFDC8qNCg== X-Authority-Analysis: v=2.4 cv=PqcG/AM3 c=1 sm=1 tr=0 ts=6add74cf cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=hAI97D9Htgy7VLTQvtAA:9 a=4Q4zU7iZy6iiv8wZ:21 a=QEXdDO2ut3YA:10 a=O8hF6Hzn-FEA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-ORIG-GUID: ua4MSSc6qQtY9UXMh_02TIkHHgwIC-vZ X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI1MDAxMiBTYWx0ZWRfX3hKaPSJ5l19a aU5Z5F67t2/ASwmnuwRoKhoF0DRjFRROnPCZyntxF0tew8S1/vD/mGF8f0UMfjiriTghyViPjOJ R5/StRWB8CAOHSTUvSSb11gRBDm9LxM= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-25_01,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 adultscore=0 spamscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 phishscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610250012 Add support for the CSID 1080 hardware found on the Kaanapali SoC. Introduce the CSID 1080 hardware resource descriptions and implement the hardware-specific register programming, reset sequence, and BUF_DONE interrupt handling. CSID 1080 uses separate registers for RUP and AUP updates, with a SET register used to commit them. Extend the CSID interface to support this scheme while retaining the legacy combined reg_update mechanism. Also define the INFO_INPUT_EOF and INFO_CAMIF_EOF bits in the per-RDI IRQ status register alongside the existing SOF bits, as well as TOP_IRQ_STATUS_RDI_OFFSET for RDI0 in the top-level IRQ registers. These definitions are added for completeness and don't enable SOF or EOF interrupts. Reviewed-by: Bryan O'Donoghue Co-developed-by: Atiya Kailany Signed-off-by: Atiya Kailany Signed-off-by: Hangxiang Ma --- drivers/media/platform/qcom/camss/Makefile | 1 + .../media/platform/qcom/camss/camss-csid-1080.c | 402 +++++++++++++++++++++ drivers/media/platform/qcom/camss/camss-csid.h | 9 +- drivers/media/platform/qcom/camss/camss.c | 75 ++++ 4 files changed, 486 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/Makefile b/drivers/media/platform/qcom/camss/Makefile index 27898b3cc7d3..218ba3a95939 100644 --- a/drivers/media/platform/qcom/camss/Makefile +++ b/drivers/media/platform/qcom/camss/Makefile @@ -8,6 +8,7 @@ qcom-camss-objs += \ camss-csid-4-7.o \ camss-csid-340.o \ camss-csid-680.o \ + camss-csid-1080.o \ camss-csid-gen2.o \ camss-csid-gen3.o \ camss-csiphy.o \ diff --git a/drivers/media/platform/qcom/camss/camss-csid-1080.c b/drivers/media/platform/qcom/camss/camss-csid-1080.c new file mode 100644 index 000000000000..9830fa0f8d24 --- /dev/null +++ b/drivers/media/platform/qcom/camss/camss-csid-1080.c @@ -0,0 +1,402 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * camss-csid-1080.c + * + * Qualcomm MSM Camera Subsystem - CSID (CSI Decoder) Module + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +#include +#include +#include +#include +#include +#include + +#include "camss.h" +#include "camss-csid.h" +#include "camss-csid-gen3.h" + +/* Reset and Command Registers */ +#define CSID_RST_CFG 0x108 +#define RST_MODE BIT(0) +#define RST_LOCATION BIT(4) + +/* Reset and Command Registers */ +#define CSID_RST_CMD 0x10C +#define SELECT_HW_RST BIT(0) +#define SELECT_IRQ_RST BIT(2) +#define CSID_IRQ_CMD 0x110 +#define IRQ_CMD_CLEAR BIT(0) + +/* Register Update Commands, RUP/AUP */ +#define CSID_RUP_CMD 0x114 +#define CSID_AUP_CMD 0x118 +#define CSID_RUP_AUP_RDI(rdi) (BIT(8) << (rdi)) +#define CSID_RUP_AUP_CMD 0x11C +#define RUP_SET BIT(0) +#define MUP BIT(4) + +/* Top level interrupt registers */ +#define CSID_TOP_IRQ_STATUS 0x180 +#define CSID_TOP_IRQ_MASK 0x184 +#define CSID_TOP_IRQ_CLEAR 0x188 +#define INFO_RST_DONE BIT(0) +#define CSI2_RX_IRQ_STATUS BIT(2) +#define BUF_DONE_IRQ_STATUS BIT(3) +#define TOP_IRQ_STATUS_RDI_OFFSET 16 + +/* Buffer done interrupt registers */ +#define CSID_BUF_DONE_IRQ_STATUS 0x1A0 +#define BUF_DONE_IRQ_STATUS_RDI_OFFSET 16 +#define CSID_BUF_DONE_IRQ_MASK 0x1A4 +#define CSID_BUF_DONE_IRQ_CLEAR 0x1A8 +#define CSID_BUF_DONE_IRQ_SET 0x1AC + +/* CSI2 RX interrupt registers */ +#define CSID_CSI2_RX_IRQ_STATUS 0x1B0 +#define CSID_CSI2_RX_IRQ_MASK 0x1B4 +#define CSID_CSI2_RX_IRQ_CLEAR 0x1B8 +#define CSID_CSI2_RX_IRQ_SET 0x1BC + +/* CSI2 RX Configuration */ +#define CSID_CSI2_RX_CFG0 0x880 +#define CSI2_RX_CFG0_NUM_ACTIVE_LANES 0 +#define CSI2_RX_CFG0_DL0_INPUT_SEL 4 +#define CSI2_RX_CFG0_PHY_NUM_SEL 20 +#define CSI2_RX_CFG0_PHY_SEL_BASE_IDX 1 +#define CSID_CSI2_RX_CFG1 0x884 +#define CSI2_RX_CFG1_ECC_CORRECTION_EN BIT(0) +#define CSI2_RX_CFG1_VC_MODE BIT(2) + +#define MSM_CSID_MAX_SRC_STREAMS_1080 (csid_is_lite(csid) ? 4 : 5) + +/* RDI Configuration */ +#define CSID_RDI_CFG0(rdi) (csid_is_lite(csid) ?\ + (0x3080 + 0x200 * (rdi)) :\ + (0x5480 + 0x200 * (rdi))) +#define RDI_CFG0_RETIME_BS BIT(5) +#define RDI_CFG0_TIMESTAMP_EN BIT(6) +#define RDI_CFG0_TIMESTAMP_STB_SEL BIT(8) +#define RDI_CFG0_DECODE_FORMAT 12 +#define RDI_CFG0_DT 16 +#define RDI_CFG0_VC 22 +#define RDI_CFG0_EN BIT(31) + +/* RDI Control and Configuration */ +#define CSID_RDI_CTRL(rdi) (csid_is_lite(csid) ?\ + (0x3088 + 0x200 * (rdi)) :\ + (0x5488 + 0x200 * (rdi))) +#define RDI_CTRL_START_CMD BIT(0) + +#define CSID_RDI_CFG1(rdi) (csid_is_lite(csid) ?\ + (0x3094 + 0x200 * (rdi)) :\ + (0x5494 + 0x200 * (rdi))) +#define RDI_CFG1_DROP_H_EN BIT(5) +#define RDI_CFG1_DROP_V_EN BIT(6) +#define RDI_CFG1_CROP_H_EN BIT(7) +#define RDI_CFG1_CROP_V_EN BIT(8) +#define RDI_CFG1_PACKING_FORMAT_MIPI BIT(15) + +/* RDI Pixel Store Configuration */ +#define CSID_RDI_PIX_STORE_CFG0(rdi) (0x5498 + 0x200 * (rdi)) +#define RDI_PIX_STORE_CFG0_EN BIT(0) +#define RDI_PIX_STORE_CFG0_MIN_HBI 1 + +/* RDI IRQ Status in wrapper */ +#define CSID_CSI2_RDIN_IRQ_STATUS(rdi) (0x224 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_MASK(rdi) (0x228 + (0x10 * (rdi))) +#define CSID_CSI2_RDIN_IRQ_CLEAR(rdi) (0x22C + (0x10 * (rdi))) +#define INFO_RUP_DONE BIT(23) +#define INFO_INPUT_SOF BIT(12) +#define INFO_INPUT_EOF BIT(9) +#define INFO_CAMIF_SOF BIT(4) +#define INFO_CAMIF_EOF BIT(3) + +static void __csid_aup_rup_trigger(struct csid_device *csid) +{ + /* trigger SET in combined register */ + writel(RUP_SET, csid->base + CSID_RUP_AUP_CMD); +} + +static void __csid_addr_update(struct csid_device *csid, int port_id) +{ + csid->aup_update |= CSID_RUP_AUP_RDI(port_id); + writel(csid->aup_update, csid->base + CSID_AUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_addr_update_clear(struct csid_device *csid, int port_id) +{ + csid->aup_update &= ~CSID_RUP_AUP_RDI(port_id); +} + +static void __csid_reg_update(struct csid_device *csid, int port_id) +{ + csid->rup_update |= CSID_RUP_AUP_RDI(port_id); + writel(csid->rup_update, csid->base + CSID_RUP_CMD); + + __csid_aup_rup_trigger(csid); +} + +static void __csid_reg_update_clear(struct csid_device *csid, int port_id) +{ + csid->rup_update &= ~CSID_RUP_AUP_RDI(port_id); +} + +static void __csid_configure_rx(struct csid_device *csid, + struct csid_phy_config *phy) +{ + u8 lane_cnt = phy->lane_cnt; + int val; + + if (!lane_cnt) + lane_cnt = 4; + + val = (lane_cnt - 1) << CSI2_RX_CFG0_NUM_ACTIVE_LANES; + val |= phy->lane_assign << CSI2_RX_CFG0_DL0_INPUT_SEL; + val |= (phy->csiphy_id + CSI2_RX_CFG0_PHY_SEL_BASE_IDX) + << CSI2_RX_CFG0_PHY_NUM_SEL; + writel(val, csid->base + CSID_CSI2_RX_CFG0); + + val = CSI2_RX_CFG1_ECC_CORRECTION_EN; + writel(val, csid->base + CSID_CSI2_RX_CFG1); +} + +static void __csid_configure_rx_vc(struct csid_device *csid, int vc) +{ + int val; + + if (vc > 3) { + val = readl(csid->base + CSID_CSI2_RX_CFG1); + val |= CSI2_RX_CFG1_VC_MODE; + writel(val, csid->base + CSID_CSI2_RX_CFG1); + } +} + +static void __csid_ctrl_rdi(struct csid_device *csid, int enable, u8 rdi) +{ + int val = 0; + + if (enable) + val = RDI_CTRL_START_CMD; + + writel(val, csid->base + CSID_RDI_CTRL(rdi)); +} + +static void __csid_configure_rdi_pix_store(struct csid_device *csid, u8 rdi) +{ + u32 val; + + /* + * Configure pixel store to allow absorption of hblanking or idle time. + * This helps with horizontal crop and prevents line buffer conflicts. + * Reset state is 0x8 which has MIN_HBI=4, we keep the default MIN_HBI + * and just enable the pixel store functionality. + */ + val = (4 << RDI_PIX_STORE_CFG0_MIN_HBI) | RDI_PIX_STORE_CFG0_EN; + writel(val, csid->base + CSID_RDI_PIX_STORE_CFG0(rdi)); +} + +static void __csid_configure_rdi_stream(struct csid_device *csid, u8 enable, u8 port, u8 vc) +{ + u8 lane_cnt = csid->phy.lane_cnt; + u32 val; + + /* Source pads matching RDI channels on hardware. + * E.g. Pad 1 -> RDI0, Pad 2 -> RDI1, etc. + */ + struct v4l2_mbus_framefmt *input_format = &csid->fmt[MSM_CSID_PAD_FIRST_SRC + port]; + const struct csid_format_info *format = csid_get_fmt_entry(csid->res->formats->formats, + csid->res->formats->nformats, + input_format->code); + + if (!lane_cnt) + lane_cnt = 4; + + val = RDI_CFG0_TIMESTAMP_EN; + val |= RDI_CFG0_TIMESTAMP_STB_SEL; + val |= RDI_CFG0_RETIME_BS; + + /* note: for non-RDI path, this should be format->decode_format */ + val |= DECODE_FORMAT_PAYLOAD_ONLY << RDI_CFG0_DECODE_FORMAT; + val |= vc << RDI_CFG0_VC; + val |= format->data_type << RDI_CFG0_DT; + writel(val, csid->base + CSID_RDI_CFG0(port)); + + val = RDI_CFG1_PACKING_FORMAT_MIPI; + writel(val, csid->base + CSID_RDI_CFG1(port)); + + /* Configure pixel store using dedicated register in 1080 */ + if (!csid_is_lite(csid)) + __csid_configure_rdi_pix_store(csid, port); + + val = 0; + writel(val, csid->base + CSID_RDI_CTRL(port)); + + val = readl(csid->base + CSID_RDI_CFG0(port)); + + if (enable) + val |= RDI_CFG0_EN; + + writel(val, csid->base + CSID_RDI_CFG0(port)); +} + +static void csid_configure_stream(struct csid_device *csid, u8 enable) +{ + u8 i, k; + + __csid_configure_rx(csid, &csid->phy); + + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { + if (csid->phy.en_vc & BIT(i)) { + __csid_configure_rdi_stream(csid, enable, i, 0); + __csid_configure_rx_vc(csid, 0); + + for (k = 0; k < CAMSS_INIT_BUF_COUNT; k++) + __csid_addr_update(csid, i); + + __csid_reg_update(csid, i); + + __csid_ctrl_rdi(csid, enable, i); + } + } +} + +static int csid_configure_testgen_pattern(struct csid_device *csid, s32 val) +{ + return 0; +} + +static void csid_subdev_reg_update(struct csid_device *csid, int port_id, bool is_clear) +{ + if (is_clear) + __csid_reg_update_clear(csid, port_id); + else + __csid_reg_update(csid, port_id); +} + +static void csid_subdev_addr_update(struct csid_device *csid, int port_id, bool is_clear) +{ + if (is_clear) + __csid_addr_update_clear(csid, port_id); + else + __csid_addr_update(csid, port_id); +} + +/** + * csid_isr - CSID module interrupt service routine + * @irq: Interrupt line + * @dev: CSID device + * + * Return IRQ_HANDLED on success + */ +static irqreturn_t csid_isr(int irq, void *dev) +{ + struct csid_device *csid = dev; + u32 val, buf_done_val; + u8 reset_done; + int i; + + val = readl(csid->base + CSID_TOP_IRQ_STATUS); + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + + reset_done = val & INFO_RST_DONE; + + buf_done_val = readl(csid->base + CSID_BUF_DONE_IRQ_STATUS); + writel(buf_done_val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { + if (csid->phy.en_vc & BIT(i)) { + val = readl(csid->base + CSID_CSI2_RDIN_IRQ_STATUS(i)); + writel(val, csid->base + CSID_CSI2_RDIN_IRQ_CLEAR(i)); + + if (val & INFO_RUP_DONE) { + __csid_addr_update_clear(csid, i); + __csid_reg_update_clear(csid, i); + } + + if (buf_done_val & BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i)) + camss_buf_done(csid->camss, csid->id, i); + } + } + + val = IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + if (reset_done) + complete(&csid->reset_complete); + + return IRQ_HANDLED; +} + +/** + * csid_reset - Trigger reset on CSID module and wait to complete + * @csid: CSID device + * + * Return 0 on success or a negative error code otherwise + */ +static int csid_reset(struct csid_device *csid) +{ + unsigned long time; + u32 val; + int i; + + reinit_completion(&csid->reset_complete); + + val = INFO_RST_DONE | BUF_DONE_IRQ_STATUS; + writel(val, csid->base + CSID_TOP_IRQ_CLEAR); + writel(val, csid->base + CSID_TOP_IRQ_MASK); + + val = 0; + for (i = 0; i < MSM_CSID_MAX_SRC_STREAMS_1080; i++) { + if (csid->phy.en_vc & BIT(i)) { + /* + * Only need to clear buf done IRQ status here, + * RUP done IRQ status will be cleared once isr + * strobe generated by CSID_RST_CMD + */ + val |= BIT(BUF_DONE_IRQ_STATUS_RDI_OFFSET + i); + } + } + writel(val, csid->base + CSID_BUF_DONE_IRQ_CLEAR); + writel(val, csid->base + CSID_BUF_DONE_IRQ_MASK); + + /* Clear all IRQ status with CLEAR bits set */ + val = IRQ_CMD_CLEAR; + writel(val, csid->base + CSID_IRQ_CMD); + + val = RST_LOCATION | RST_MODE; + writel(val, csid->base + CSID_RST_CFG); + + val = SELECT_HW_RST | SELECT_IRQ_RST; + writel(val, csid->base + CSID_RST_CMD); + + time = wait_for_completion_timeout(&csid->reset_complete, + msecs_to_jiffies(CSID_RESET_TIMEOUT_MS)); + + if (!time) { + dev_err(csid->camss->dev, "CSID reset timeout\n"); + return -EIO; + } + + return 0; +} + +static void csid_subdev_init(struct csid_device *csid) +{ + csid->testgen.nmodes = CSID_PAYLOAD_MODE_DISABLED; +} + +const struct csid_hw_ops csid_ops_1080 = { + .configure_stream = csid_configure_stream, + .configure_testgen_pattern = csid_configure_testgen_pattern, + .hw_version = csid_hw_version, + .isr = csid_isr, + .reset = csid_reset, + .src_pad_code = csid_src_pad_code, + .subdev_init = csid_subdev_init, + .reg_update = csid_subdev_reg_update, + .addr_update = csid_subdev_addr_update, +}; diff --git a/drivers/media/platform/qcom/camss/camss-csid.h b/drivers/media/platform/qcom/camss/camss-csid.h index 2f7e593defed..603621c16315 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.h +++ b/drivers/media/platform/qcom/camss/camss-csid.h @@ -162,7 +162,13 @@ struct csid_device { void __iomem *base; u32 irq; char irq_name[30]; - u32 reg_update; + union { + u32 reg_update; + struct { + u32 rup_update; + u32 aup_update; + }; + }; struct camss_clock *clock; int nclocks; struct regulator_bulk_data *supplies; @@ -224,6 +230,7 @@ extern const struct csid_hw_ops csid_ops_4_1; extern const struct csid_hw_ops csid_ops_4_7; extern const struct csid_hw_ops csid_ops_340; extern const struct csid_hw_ops csid_ops_680; +extern const struct csid_hw_ops csid_ops_1080; extern const struct csid_hw_ops csid_ops_gen2; extern const struct csid_hw_ops csid_ops_gen3; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 0358ee384012..7acace363fc2 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -83,6 +83,79 @@ static const struct camss_subdev_resources csiphy_res_kaanapali[] = { }, }; +static const struct camss_subdev_resources csid_res_kaanapali[] = { + /* CSID0 */ + { + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_1080, + .formats = &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_1080, + .formats = &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .clock = { "csid", "csid_csiphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .csid = { + .is_lite = false, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_1080, + .formats = &csid_formats_gen2 + } + }, + /* CSID_LITE0 */ + { + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid_lite0" }, + .interrupt = { "csid_lite0" }, + .csid = { + .is_lite = true, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_1080, + .formats = &csid_formats_gen2 + } + }, + /* CSID_LITE1 */ + { + .clock = { "vfe_lite_csid", "vfe_lite_cphy_rx" }, + .clock_rate = { { 400000000, 480000000 }, + { 400000000, 480000000 } }, + .reg = { "csid_lite1" }, + .interrupt = { "csid_lite1" }, + .csid = { + .is_lite = true, + .parent_dev_ops = &vfe_parent_dev_ops, + .hw_ops = &csid_ops_1080, + .formats = &csid_formats_gen2 + } + } +}; + static const struct resources_icc icc_res_kaanapali[] = { { .name = "ahb", @@ -5652,9 +5725,11 @@ static const struct camss_resources kaanapali_resources = { .version = CAMSS_KAANAPALI, .pd_name = "top", .csiphy_res = csiphy_res_kaanapali, + .csid_res = csid_res_kaanapali, .icc_res = icc_res_kaanapali, .icc_path_num = ARRAY_SIZE(icc_res_kaanapali), .csiphy_num = ARRAY_SIZE(csiphy_res_kaanapali), + .csid_num = ARRAY_SIZE(csid_res_kaanapali), }; static const struct camss_resources msm8916_resources = { -- 2.34.1