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[63.152.17.145]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-70b9e1fa334sm824552eaf.9.2026.10.23.20.02.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2026 20:02:33 -0700 (PDT) From: Jeff Roach To: Nabige Aala Cc: Vinod Koul , Neil Armstrong , Manivannan Sadhasivam , Dmitry Baryshkov , Wesley Cheng , Abel Vesa , Johan Hovold , Bjorn Andersson , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Ritesh Kumar , Mahadevan P Subject: Re: [PATCH v5 10/11] phy: qualcomm: qmp-combo: Fix Glymur v8 DP PHY init and configure sequences Date: Fri, 23 Oct 2026 22:01:35 -0500 Message-ID: <20261024030142.13643-12-jeff.roach0@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261001-glymur-phy-v3-v5-10-3848c2615d5a@oss.qualcomm.com> References: <20261001-glymur-phy-v3-v5-10-3848c2615d5a@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Thu, 01 Oct 2026 15:04:27 +0530, Nabige Aala wrote: > Update qmp_v8_dp_aux_init(): > - Add CLK_FWD_CONFIG_1 initialization (0x3f) before power-down control > - Replace PSR_PWRDN with LANE_0_1_PWRDN and LANE_2_3_PWRDN in PD_CTL > to correctly power down the data lanes > - Correct BIAS_EN_CLKBUFLR_EN value from 0x1c to 0x17 > [...] Tested-by: Jeff Roach # HP OmniBook X 16 (Mahua)