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([178.66.130.53]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a08643dsm46716525e9.4.2026.10.24.07.09.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 07:09:05 -0700 (PDT) From: Artem Shimko To: linux@roeck-us.net, p.zabel@pengutronix.de, Sergey.Semin@baikalelectronics.ru, mika.westerberg@linux.intel.com, andi.shyti@kernel.org, iav@iav.lv, tzungbi@kernel.org Cc: Artem Shimko , wim@linux-watchdog.org, linux-watchdog@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v4 2/2] watchdog: dw_wdt: manage reset line during system suspend/resume Date: Sat, 24 Oct 2026 17:08:51 +0300 Message-ID: <20261024140854.25664-3-a.shimko.dev@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261024140854.25664-1-a.shimko.dev@gmail.com> References: <20261024140854.25664-1-a.shimko.dev@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The watchdog controller reset line is not currently managed during system suspend/resume. This can lead to an inconsistent hardware state when resuming from suspend, as the controller may not be properly reinitialized. Assert the reset line before disabling clocks during suspend to ensure the controller is held in reset while power is gated. During resume, deassert the reset after clocks are enabled and before restoring register state to guarantee the controller is properly initialized. Tested-by: Igor Velkov Reviewed-by: Tzung-Bi Shih Signed-off-by: Artem Shimko --- drivers/watchdog/dw_wdt.c | 25 ++++++++++++++++++++----- 1 file changed, 20 insertions(+), 5 deletions(-) diff --git a/drivers/watchdog/dw_wdt.c b/drivers/watchdog/dw_wdt.c index ebd27ee684d1..684e0cb104c3 100644 --- a/drivers/watchdog/dw_wdt.c +++ b/drivers/watchdog/dw_wdt.c @@ -378,10 +378,15 @@ static irqreturn_t dw_wdt_irq(int irq, void *devid) static int dw_wdt_suspend(struct device *dev) { struct dw_wdt *dw_wdt = dev_get_drvdata(dev); + int err; dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); + err = reset_control_assert(dw_wdt->rst); + if (err) + return err; + clk_disable_unprepare(dw_wdt->pclk); clk_disable_unprepare(dw_wdt->clk); @@ -391,16 +396,19 @@ static int dw_wdt_suspend(struct device *dev) static int dw_wdt_resume(struct device *dev) { struct dw_wdt *dw_wdt = dev_get_drvdata(dev); - int err = clk_prepare_enable(dw_wdt->clk); + int err; + err = clk_prepare_enable(dw_wdt->clk); if (err) return err; err = clk_prepare_enable(dw_wdt->pclk); - if (err) { - clk_disable_unprepare(dw_wdt->clk); - return err; - } + if (err) + goto unprepare_clk; + + err = reset_control_deassert(dw_wdt->rst); + if (err) + goto unprepare_pclk; writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET); writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET); @@ -408,6 +416,13 @@ static int dw_wdt_resume(struct device *dev) dw_wdt_ping(&dw_wdt->wdd); return 0; + +unprepare_pclk: + clk_disable_unprepare(dw_wdt->pclk); +unprepare_clk: + clk_disable_unprepare(dw_wdt->clk); + + return err; } static DEFINE_SIMPLE_DEV_PM_OPS(dw_wdt_pm_ops, dw_wdt_suspend, dw_wdt_resume); -- 2.43.0