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Wysocki" , linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] genirq/PM: Re-enable chained interrupts after hibernation Date: Sat, 24 Oct 2026 22:46:21 +0800 Message-ID: <20261024144623.112667-1-zhuling2709@phytium.com.cn> X-Mailer: git-send-email 2.43.0 In-Reply-To: <87mrtr1p8i.ffs@fw13> References: <87mrtr1p8i.ffs@fw13> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID:AQAAf8DwwXPDxNxqm+jwAA--.12400S3 X-CM-SenderInfo: x2kxzxlqjsliuz6sx5pwlxzhxfrphubq/1tbiAQAPAWrXwUoEpgAms9 Authentication-Results: hzbj-icmmx-7; spf=neutral smtp.mail=zhuling270 9@phytium.com.cn; X-Coremail-Antispam: 1Uk129KBjvJXoW7CF1rtF4kur18JF4xCryDKFg_yoW8ArWfpF ZrGrZYvrWkJw10gan7Gw4IvFyxGrs3Gw4UXwn3K34DZw4rCFyvyFnag3W3Za4UCrZ3Z3W2 vw4Yg3WfCF4DCFJanT9S1TB71UUUUUDqnTZGkaVYY2UrUUUUj1kv1TuYvTs0mT0YCTnIWj DUYxn0WfASr-VFAU7a7-sFnT9fnUUIcSsGvfJ3UbIYCTnIWIevJa73UjIFyTuYvj4RJUUU UUUUU Hi Thomas,=0D =0D Thank you for the review. I am withdrawing the previous genirq/PM=0D proposal. Please do not apply it: forcing chained IRQs through generic=0D resume treats the symptom rather than restoring controller state.=0D =0D I have since reproduced the failure on the Phytium E2000Q platform=0D using upstream base 17bb0e2f6c8043f70a693a5f3797471cbed354c8.=0D GPIOLIB is disabled and no vendor GPIO driver is involved. An independent=0D module registers either an ordinary or chained handler on an idle=0D GICv3 SPI (INTID 189) and injects a real GIC pending event before and=0D after hibernation. It has no PM callbacks or automatic recovery.=0D =0D On separate fresh boots, the ordinary IRQ delivers both injections.=0D The chained IRQ delivers only the first. After real S4, its descriptor=0D still reports started=3D1, disabled=3D0 and sw_masked=3D0, but the hardware= =0D enable bit is clear and the second event remains pending. An explicit=0D unmask delivers that queued event without another injection or handler=0D reinstallation.=0D =0D A GICv3-side SPI context save/restore revision passes the same test=0D in both modes: hits=3D2, injected=3D2, unexpected=3D0 and rescued=3D0. Each= =0D mode was tested for one real S4 cycle on a fresh boot, with CPU0,=0D disk=3Dshutdown and pm_test=3Dnone. No introducing commit is claimed.=0D =0D The test kernels contain a separate 8-line USB host enablement, but=0D the unpatched test leaves the IRQ/GIC/PM paths unchanged. The test=0D module sets the out-of-tree taint bit; both conditions are disclosed=0D in the new cover letter.=0D =0D I will send v2 as a separate thread, linking this discussion. It=0D preserves SPI distributor configuration in GICv3 and does not change=0D genirq policy. It is not a claim of complete GICv3/ITS S4 support.=0D =0D Thanks,=0D Zhu Ling=0D