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charset="utf-8" Message-Id: <20261026-msm-dpu-res-clean-v2-1-3d864435186e@gmail.com> References: <20261026-msm-dpu-res-clean-v2-0-3d864435186e@gmail.com> In-Reply-To: <20261026-msm-dpu-res-clean-v2-0-3d864435186e@gmail.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Xi Zhang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793046364; l=2413; i=xz.ca.cn@gmail.com; s=20261026; h=from:subject:message-id; bh=XV5yIGRicisWHnZm/blBrd+eV6OtBhD/12tGnVobzAE=; b=PC8rCKcVBdPqI+8YugF/JK3f2ZJoK/+mL56ZMTYea2y7srn3rB74fUnnoW9F8vEyXVAqrCM8q VE1DcpN1W9pDxN4Xt9VuTInL1zi5OYgy7EqvaOEC6pTnu6kDrmKZzJQ X-Developer-Key: i=xz.ca.cn@gmail.com; a=ed25519; pk=aRUll5L3eJbwG8Y4BO9uySKGzm+Uy+Ccei9prnRVZRs= X-Endpoint-Received: by B4 Relay for xz.ca.cn@gmail.com/20261026 with auth_id=1328 X-Original-From: Xi Zhang Reply-To: xz.ca.cn@gmail.com Content-Transfer-Encoding: 7bit From: Xi Zhang While this is not currently the case, it may be possible that topology for cwb and dsc resource requirements change between mode set in the future. e.g. when dsc support is added to DisplayPort, dsc may be optionally enabled and disabled between different modes due to bandwidth requirements. Set unassigned resource slots to NULL on topology update to avoid issues in the future. It's good practice to do so anyway. Signed-off-by: Xi Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 0a6be69a3e83..8d2b4d2726f2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -1205,9 +1205,13 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, ARRAY_SIZE(hw_pp)); } - for (i = 0; i < num_cwb; i++) { - dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]); - cwb_mask |= BIT(dpu_enc->hw_cwb[i]->idx - CWB_0); + for (i = 0; i < ARRAY_SIZE(dpu_enc->hw_cwb); i++) { + if (i < num_cwb) { + dpu_enc->hw_cwb[i] = to_dpu_hw_cwb(hw_cwb[i]); + cwb_mask |= BIT(dpu_enc->hw_cwb[i]->idx - CWB_0); + } else { + dpu_enc->hw_cwb[i] = NULL; + } } dpu_enc->cwb_mask = cwb_mask; @@ -1215,16 +1219,20 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, num_ctl = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->crtc, DPU_HW_BLK_CTL, hw_ctl, ARRAY_SIZE(hw_ctl)); - for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) + for (i = 0; i < ARRAY_SIZE(dpu_enc->hw_pp); i++) dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i]) : NULL; num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, drm_enc->crtc, DPU_HW_BLK_DSC, hw_dsc, ARRAY_SIZE(hw_dsc)); - for (i = 0; i < num_dsc; i++) { - dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); - dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); + for (i = 0; i < ARRAY_SIZE(dpu_enc->hw_dsc); i++) { + if (i < num_dsc) { + dpu_enc->hw_dsc[i] = to_dpu_hw_dsc(hw_dsc[i]); + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0); + } else { + dpu_enc->hw_dsc[i] = NULL; + } } dpu_enc->dsc_mask = dsc_mask; -- 2.55.0