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Mon, 26 Oct 2026 20:26:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793046366; bh=jKjNavX4bHbKF/qvrtUQ5ioa60gUilED0q32oHaX4e8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To; b=bNdiq+nxwg9MGEvO6RZqH0HmaLbmx+lKuzLsB07AL5ZSRjfqLVPKkLev3M0OJg41C JMTXfK9XzREeijz3DE3IXmEMB0WyOd7yjYaFqkA7vSYJeAzBd4TNSvm33XTn+pQDHV 15Vha97pwhfgxk1tTvGvmFKsfEzmrloxHidWJa1jFl5Z+NnvjJkulrVAtrBorbSPvK BNdNSBB3Q1/0sLJeMtXkqn5IZ6jMxIA7i2Ax11xyXNYeKQRzmn/XP9mtAZt3pjFdky 6kN+7WkJYzaPvo7ptrQDL9nTY5h6Z0foUXiuist0YsVydBasUW4n6RN6CynX9FRhvl OvKi3j8ItjI9Q== Received: from nexus.subspace.kernel.org (localhost [IPv6:::1]) by lkml.kernel.org (Postfix) with ESMTP id DF49444E95; Mon, 26 Oct 2026 20:26:04 +0000 (UTC) From: Xi Zhang via B4 Relay Date: Mon, 26 Oct 2026 17:25:44 -0300 Subject: [PATCH v2 3/6] drm/msm/dpu: use common helper cleanup function in cmd mode disable X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-Id: <20261026-msm-dpu-res-clean-v2-3-3d864435186e@gmail.com> References: <20261026-msm-dpu-res-clean-v2-0-3d864435186e@gmail.com> In-Reply-To: <20261026-msm-dpu-res-clean-v2-0-3d864435186e@gmail.com> To: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Xi Zhang X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793046364; l=2525; i=xz.ca.cn@gmail.com; s=20261026; h=from:subject:message-id; bh=XhOd7j42hxYmVLxXb4nr7ytDGGzBgeEYP3Gif2p9Ajo=; b=e+J51x5c64ypvjwE1MQ2QKGu9yAPbPv6lxkaLyn/zLFZ2cMCcFtUkEjW3LpXgDrk6V+km22HW 7L/JXrcXEOfDemtZjChGE7ywZEmTGjMt1OawtJ6VfQ0RmIQo/sVya8b X-Developer-Key: i=xz.ca.cn@gmail.com; a=ed25519; pk=aRUll5L3eJbwG8Y4BO9uySKGzm+Uy+Ccei9prnRVZRs= X-Endpoint-Received: by B4 Relay for xz.ca.cn@gmail.com/20261026 with auth_id=1328 X-Original-From: Xi Zhang Reply-To: xz.ca.cn@gmail.com Content-Transfer-Encoding: 7bit From: Xi Zhang cmd mode encoder previously did not clean up dsc, or LMs during disable. Change to use the common dpu_encoder_helper_phys_cleanup function for cmd mode disable. Also do not set intf_cfg.mode_3d during disable: dpu_encoder_helper_get_3d_blend_mode accesses drm_encoder->crtc->state directly so intf_cfg.mode_3d weren't set to expected value for disable. intf_cfg.mode_3d is also ignored by ctl->ops.reset_intf_cfg. Signed-off-by: Xi Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 10 +--------- 2 files changed, 3 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 81b983ecffbb..d967deb34c77 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2335,8 +2335,8 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) dpu_enc->dsc = NULL; } - intf_cfg.stream_sel = 0; /* Don't care value for video mode */ - intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc); + intf_cfg.stream_sel = 0; /* Ignored by reset_intf_cfg */ + intf_cfg.mode_3d = 0; /* Ignored by reset_intf_cfg */ intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc); intf_cfg.cwb = dpu_enc->cwb_mask; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 45079ee59cf6..111f9dd5e053 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -538,7 +538,6 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) { struct dpu_encoder_phys_cmd *cmd_enc = to_dpu_encoder_phys_cmd(phys_enc); - struct dpu_hw_ctl *ctl; if (phys_enc->enable_state == DPU_ENC_DISABLED) { DPU_ERROR_CMDENC(cmd_enc, "already disabled\n"); @@ -566,14 +565,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc) phys_enc->hw_pp->ops.disable_tearcheck(phys_enc->hw_pp); } - if (phys_enc->hw_intf->ops.bind_pingpong_blk) { - phys_enc->hw_intf->ops.bind_pingpong_blk( - phys_enc->hw_intf, - PINGPONG_NONE); - - ctl = phys_enc->hw_ctl; - ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx); - } + dpu_encoder_helper_phys_cleanup(phys_enc); phys_enc->enable_state = DPU_ENC_DISABLED; } -- 2.55.0