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[187.126.110.245]) by smtp.gmail.com with ESMTPSA id ada2fe7eead31-7ce5e2baf56sm6140100137.11.2026.10.25.20.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Oct 2026 20:50:48 -0700 (PDT) From: Felipe Calliari To: linux-media@vger.kernel.org Cc: Sakari Ailus , Hans de Goede , Bryan O'Donoghue , Mauro Carvalho Chehab , Dan Scally , Tomas Moro , linux-kernel@vger.kernel.org, Felipe Calliari Subject: [PATCH v4 3/5] media: ov02c10: Split the PLL registers off the mode tables Date: Mon, 26 Oct 2026 00:50:13 -0300 Message-ID: <20261026035015.110903-4-calliarifelipe@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261026035015.110903-1-calliarifelipe@gmail.com> References: <20260923234100.318151-1-calliarifelipe@gmail.com> <20261026035015.110903-1-calliarifelipe@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Both per-lane tables end with the same "plls" block, which sets 0x0303, 0x0305 and 0x0316 to 0x05, 0x90 and 0x90, overriding the 0x06 and 0xe0 that the common mode table writes to 0x0303 and 0x0305. These PLL settings determine the link frequency and the pixel rate, not the lane count. Move the block into a table of its own, and tie it to the link frequency through a new link_freq_configs[] array, indexed like link_freq_menu_items[]. Write the table right after the common table, so it still overrides 0x0303 and 0x0305, and before the per-lane table, so 0x3016 is still written after it. This prepares for link frequencies obtained from other external clock rates than 19.2 MHz. No functional change intended: the same values are written to the same registers, and the common table is left unchanged. Only the per-lane registers other than 0x3016 are now written after the PLL registers instead of before them. Signed-off-by: Felipe Calliari --- Notes: Changes in v4: - Tie the PLL table to the link frequency, through a link_freq_configs[] array indexed like link_freq_menu_items[], instead of naming it after the 19.2 MHz external clock (Sakari). - Leave the common table alone, including its 0x0303 = 0x06 and 0x0305 = 0xe0 writes, and only move the "plls" block of the per-lane tables, so every register write is kept (Sakari). Changes in v3: - New patch, as asked by Sakari. drivers/media/i2c/ov02c10.c | 35 +++++++++++++++++++++++++++++------ 1 file changed, 29 insertions(+), 6 deletions(-) diff --git a/drivers/media/i2c/ov02c10.c b/drivers/media/i2c/ov02c10.c index e24cd8705..62ea20dc5 100644 --- a/drivers/media/i2c/ov02c10.c +++ b/drivers/media/i2c/ov02c10.c @@ -303,10 +303,6 @@ static const struct reg_sequence sensor_1928x1092_30fps_1lane_setting[] = { {0x394e, 0x0b}, {0x4800, 0x24}, {0x5000, 0xf5}, - /* plls */ - {0x0303, 0x05}, - {0x0305, 0x90}, - {0x0316, 0x90}, {0x3016, 0x12}, }; @@ -330,11 +326,14 @@ static const struct reg_sequence sensor_1928x1092_30fps_2lane_setting[] = { {0x4d0d, 0x00}, {0x5000, 0xfd}, {0x481f, 0x30}, - /* plls */ + {0x3016, 0x32}, +}; + +/* 400 MHz link frequency from a 19.2 MHz external clock */ +static const struct reg_sequence sensor_pll_400mhz_setting[] = { {0x0303, 0x05}, {0x0305, 0x90}, {0x0316, 0x90}, - {0x3016, 0x32}, }; static const char * const ov02c10_test_pattern_menu[] = { @@ -349,6 +348,20 @@ static const s64 link_freq_menu_items[] = { OV02C10_LINK_FREQ_400MHZ, }; +struct ov02c10_link_freq_config { + /* PLL register settings, which set the link frequency */ + const struct reg_sequence *pll_settings; + int pll_settings_length; +}; + +/* Indexed like link_freq_menu_items[] */ +static const struct ov02c10_link_freq_config link_freq_configs[] = { + { + .pll_settings = sensor_pll_400mhz_setting, + .pll_settings_length = ARRAY_SIZE(sensor_pll_400mhz_setting), + }, +}; + static const struct ov02c10_mode supported_modes[] = { { .width = 1928, @@ -594,6 +607,8 @@ static int ov02c10_enable_streams(struct v4l2_subdev *sd, { const struct ov02c10_mode *mode = &supported_modes[0]; struct ov02c10 *ov02c10 = to_ov02c10(sd); + const struct ov02c10_link_freq_config *link_freq_config = + &link_freq_configs[ov02c10->link_freq_index]; const struct reg_sequence *reg_sequence; int ret, sequence_length; @@ -610,6 +625,14 @@ static int ov02c10_enable_streams(struct v4l2_subdev *sd, goto out; } + ret = regmap_multi_reg_write(ov02c10->regmap, + link_freq_config->pll_settings, + link_freq_config->pll_settings_length); + if (ret) { + dev_err(ov02c10->dev, "failed to write PLL settings\n"); + goto out; + } + reg_sequence = mode->lane_settings[ov02c10->mipi_lanes - 1]; sequence_length = mode->lane_settings_length[ov02c10->mipi_lanes - 1]; ret = regmap_multi_reg_write(ov02c10->regmap, -- 2.56.0