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CPU0 bypasses this path, leaving its IBS state stale after resume. Fix this by explicitly setting CPU0's IBS state in the syscore ->resume() callback. Fixes: efa5700ec0da ("perf/amd/ibs: Support IBS_{FETCH|OP}_CTL2[Dis] to eliminate RMW race") Signed-off-by: Ravi Bangoria Reviewed-by: Jim Mattson --- arch/x86/events/amd/ibs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c index 3531f9c23b8c..bfb51f8e184f 100644 --- a/arch/x86/events/amd/ibs.c +++ b/arch/x86/events/amd/ibs.c @@ -1948,7 +1948,7 @@ static int perf_ibs_suspend(void *data) static void perf_ibs_resume(void *data) { ibs_eilvt_setup(); - setup_APIC_ibs(); + x86_pmu_amd_ibs_starting_cpu(smp_processor_id()); } static const struct syscore_ops perf_ibs_syscore_ops = { -- 2.55.0