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Miller" , Eric Dumazet , "Jakub Kicinski" , Paolo Abeni , "Nithin Kumar Dabilpuram" , Satha Rao , vmukunda Subject: [PATCH 1/1] octeontx2-af: widen TX scheduler queue index to 11 bits Date: Mon, 26 Oct 2026 06:23:16 +0000 Message-ID: <20261026062316.754904-1-vmukunda@marvell.com> X-Mailer: git-send-email 2.25.1 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Authority-Analysis: v=2.4 cv=N+O8hG9B c=1 sm=1 tr=0 ts=6adef1d9 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=660iZSQnnn4A:10 a=VkNPw1HP01LnGYTKEx00:22 a=l0iWHRpgs5sLHlkKQ1IR:22 a=TtqV-g6YmW1Jfm2GSLaY:22 a=M5GUcnROAAAA:8 a=EuGbU4x2D8lrRcO57msA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: vq8X4tVattUWODoPTP1rj8mFN7DfhdYc X-Proofpoint-ORIG-GUID: vq8X4tVattUWODoPTP1rj8mFN7DfhdYc X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI2MDAyNSBTYWx0ZWRfX0SevdIeUcyGz SRb6620/zb4HZv+AdrJaUKycW3q97NjMbaT/qYuK//DXjDTvg5daeqIwj/uKUZrqy77sUY6WYJ/ rWvcJGflNggWYx412sCzJf6im4bZ2gY= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI2MDAyNSBTYWx0ZWRfXz193rha4JGxm 0z2slJ+QwZWEdbYZAqkEWi0FmPckN5e/JdMhSud/pz4AQdSfGnToYfA3gi9Itu/j5YLwLi4hknx vuew/XIxyPU7L/VxFrk3QdRAzM08oWdq/7saX1xbrUEMQo1NeRi3TgR0FobBjmdVzhGBDdaLE6W KICJuTHKhldUGTNplpPLIAR/n14vGV78mDn4X9ittnTajdd7zAvqpDGw5NY/7RY5V7uvNjYq7LB FPfLWc2r+ZdrFgFpiI+Z2wTnxXEDzI7JcxW1TAMEOpY3FxddPfYlqxjGtMcTT40POcYZhOv3NOP OTMOYN6Jxx9RXr+QBcRZfhD5JsLETX/NH+A6dy4qqzeeHlGrjIo1A+YrR8kdpqagVnmTRuOkEUa cmn+/pXnFSRjK/UFK453tBIvAHDMPE/xHvFB/nJc4ePvbbb+QPxb4Z26AuFnWEeLgYN8AgYCQeM j4D2B1seaWOc3MT3uCQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-26_01,2026-10-21_02,2025-10-01_01 From: Satha Rao The scheduler queue number packed above the 16-bit register offset was masked to 10 bits ([25:16]). Queue indices of 1024 and above were truncated, so configuration and readback used the wrong TX scheduler queue. The queue number is 11 bits ([26:16]). Widen TXSCHQ_IDX_MASK to 11 bits and NIX_TX_SCHQ_MASK through bit 26. Fixes: 98e09d19688c ("octeontx2-af: fix TX scheduler count") Signed-off-by: Satha Rao Signed-off-by: vmukunda --- --- drivers/net/ethernet/marvell/octeontx2/af/mbox.h | 2 +- drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h index cece197d1074..1b62f9d7f00a 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h +++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h @@ -1164,7 +1164,7 @@ struct nix_txschq_config { u8 lvl; /* SMQ/MDQ/TL4/TL3/TL2/TL1 */ u8 read; #define TXSCHQ_IDX_SHIFT 16 -#define TXSCHQ_IDX_MASK (BIT_ULL(10) - 1) +#define TXSCHQ_IDX_MASK (BIT_ULL(11) - 1) #define TXSCHQ_IDX(reg, shift) (((reg) >> (shift)) & TXSCHQ_IDX_MASK) u8 num_regs; #define MAX_REGS_PER_MBOX_MSG 20 diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c index 153eb57bad06..68cf730a8372 100644 --- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c +++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c @@ -2850,9 +2850,9 @@ static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw, } /* Register offset - [15:0] - * Scheduler Queue number - [25:16] + * Scheduler Queue number - [26:16] */ -#define NIX_TX_SCHQ_MASK GENMASK_ULL(25, 0) +#define NIX_TX_SCHQ_MASK GENMASK_ULL(26, 0) static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw, int blkaddr, struct nix_txschq_config *req, -- 2.25.1