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Mon, 26 Oct 2026 02:29:08 -0700 (PDT) Received: from GLaDOS.station ([187.13.216.220]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a5822a7sm187356525e9.11.2026.10.26.02.29.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 02:29:08 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: Frank Li , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Luan Rafael Carneiro Subject: [PATCH v1 1/1] arm64: dts: freescale: imx8mm-var-dart-sonata: Fix PCIe PHY init Date: Mon, 26 Oct 2026 10:28:58 +0100 Message-ID: <20261026092858.10591-1-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Stefano Radaelli The PCIe PHY times out during initialization on the DART-MX8M Mini with the Sonata carrier, preventing PCIe device enumeration. Add fsl,clkreq-unsupported to configure the PHY for operation without CLKREQ# support. This makes the PHY driver clear AUX_EN_OVERRIDE, allowing PHY initialization to complete. Fixes: 770aba46ea0f ("arm64: dts: imx8mm-var-dart: Add support for Variscite Sonata board") Co-developed-by: Luan Rafael Carneiro Signed-off-by: Luan Rafael Carneiro Signed-off-by: Stefano Radaelli --- arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts index 57d29a5c3821..ccc81e5b3d36 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-var-dart-sonata.dts @@ -267,6 +267,7 @@ &pcie_phy { fsl,refclk-pad-mode = ; fsl,tx-deemph-gen1 = <0x2d>; fsl,tx-deemph-gen2 = <0xf>; + fsl,clkreq-unsupported; clocks = <&pcie0_refclk>; status = "okay"; }; -- 2.47.3