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[93.34.92.187]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4a35a0cc374sm190382825e9.9.2026.10.26.02.57.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 02:57:39 -0700 (PDT) From: Christian Marangi To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 4/9] arm64: dts: airoha: en7581: add thermal sensor nodes Date: Mon, 26 Oct 2026 10:57:10 +0100 Message-ID: <20261026095727.31708-5-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261026095727.31708-1-ansuelsmth@gmail.com> References: <20261026095727.31708-1-ansuelsmth@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add thermal sensor nodes and attach them to the CPU node to control passive throttle and define critical temperature of the SoC. Signed-off-by: Christian Marangi --- arch/arm64/boot/dts/airoha/en7581.dtsi | 47 ++++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index fbc5ee47523c..58bd8b318910 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -4,6 +4,7 @@ #include #include #include +#include / { interrupt-parent = <&gic>; @@ -81,6 +82,7 @@ cpu0: cpu@0 { power-domains = <&cpufreq>; power-domain-names = "perf"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu1: cpu@1 { @@ -94,6 +96,7 @@ cpu1: cpu@1 { power-domains = <&cpufreq>; power-domain-names = "perf"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu2: cpu@2 { @@ -107,6 +110,7 @@ cpu2: cpu@2 { power-domains = <&cpufreq>; power-domain-names = "perf"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; cpu3: cpu@3 { @@ -120,6 +124,7 @@ cpu3: cpu@3 { power-domains = <&cpufreq>; power-domain-names = "perf"; next-level-cache = <&l2>; + #cooling-cells = <2>; }; l2: l2-cache { @@ -293,6 +298,39 @@ timer { ; }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + + thermal-sensors = <&thermal 0>; + + trips { + cpu_hot: cpu-hot { + temperature = <95000>; + hysteresis = <1000>; + type = "hot"; + }; + + cpu-critical { + temperature = <120000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&cpu_hot>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; + }; + }; + clk20m: clock-20000000 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -319,6 +357,15 @@ gic: interrupt-controller@9000000 { interrupts = ; }; + thermal: thermal-sensor@1efbd000 { + compatible = "airoha,en7581-thermal"; + reg = <0x0 0x1efbd000 0x0 0xd5c>; + interrupts = ; + airoha,chip-scu = <&chip_scu>; + + #thermal-sensor-cells = <0>; + }; + spi@1fa10000 { compatible = "airoha,en7581-snand"; reg = <0x0 0x1fa10000 0x0 0x140>, -- 2.55.0