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[93.34.92.187]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-4a35a0cc374sm190382825e9.9.2026.10.26.02.57.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 02:57:43 -0700 (PDT) From: Christian Marangi To: Matthias Brugger , AngeloGioacchino Del Regno , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Christian Marangi , linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 7/9] arm64: dts: airoha: en7581: add nodes for all supported uart and hsuart Date: Mon, 26 Oct 2026 10:57:13 +0100 Message-ID: <20261026095727.31708-8-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.55.0 In-Reply-To: <20261026095727.31708-1-ansuelsmth@gmail.com> References: <20261026095727.31708-1-ansuelsmth@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add all the nodes to support the existing uart and hsuart present on the SoC. Also update the compatible for the already defined uart to use the more specific UART configuration. Signed-off-by: Christian Marangi --- arch/arm64/boot/dts/airoha/en7581.dtsi | 46 +++++++++++++++++++++++++- 1 file changed, 45 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi index 760f0c3e6090..ee1633f01068 100644 --- a/arch/arm64/boot/dts/airoha/en7581.dtsi +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -470,13 +470,24 @@ fixed-link { }; }; + serial@1fbe1000 { + compatible = "airoha,an7581-hsuart"; + reg = <0x0 0x1fbe1000 0x0 0x40>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <7372800>; + + status = "disabled"; + }; + pbus_csr: syscon@1fbe3400 { compatible = "airoha,en7581-pbus-csr", "syscon"; reg = <0x0 0x1fbe3400 0x0 0xff>; }; uart1: serial@1fbf0000 { - compatible = "ns16550"; + compatible = "airoha,en7523-uart"; reg = <0x0 0x1fbf0000 0x0 0x30>; reg-io-width = <4>; reg-shift = <2>; @@ -517,6 +528,39 @@ en7581_pwm: pwm { }; }; + serial@1fbf0300 { + compatible = "airoha,en7523-uart"; + reg = <0x0 0x1fbf0300 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <7372800>; + + status = "disabled"; + }; + + serial@1fbf0600 { + compatible = "airoha,en7523-uart"; + reg = <0x0 0x1fbf0600 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <7372800>; + + status = "disabled"; + }; + + serial@1fbf0700 { + compatible = "airoha,en7523-uart"; + reg = <0x0 0x1fbf0700 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = ; + clock-frequency = <7372800>; + + status = "disabled"; + }; + i2c0: i2c@1fbf8000 { compatible = "mediatek,mt7621-i2c"; reg = <0x0 0x1fbf8000 0x0 0x100>; -- 2.55.0