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Mon, 26 Oct 2026 04:10:15 -0700 (PDT) Received: from raviolimobile.tail5f26fd.ts.net ([84.70.180.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a04ad39sm499383945e9.1.2026.10.26.04.10.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 04:10:15 -0700 (PDT) From: Fernando Rimoli To: Sergey Lebedev , Hao Yao Cc: Fernando Rimoli , Hans de Goede , Daniel Scally , Sakari Ailus , =?UTF-8?q?Ilpo=20J=C3=A4rvinen?= , platform-driver-x86@vger.kernel.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2] platform/x86: int3472: Use actual clock frequency for DSM method Date: Mon, 26 Oct 2026 11:10:10 +0000 Message-ID: <20261026111012.33347-1-fernandorimoli11@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261025162614.95385-1-lsa.uz@pm.me> References: <20251208035122.2147678-1-hao.yao@intel.com> <20261025155048.42957-1-fernandorimoli11@gmail.com> <20261025162614.95385-1-lsa.uz@pm.me> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Sergey, Hao, On 25/10/2026 16:26, Sergey Lebedev wrote: > Fernando, a run with 0 in place of 3 would tell, and your own DSDT > whether it still matches the dump. It takes 0. The DSDT on this machine (BIOS 23.102.143, 11/25/2025) still matches the dump: the clock _DSM on ICL0, ICL1 and ICL2 calls ICLK.CLKC with Arg3[1] and then ICLK.CLKF with Arg3[2], and CLKF does CLKx = (CLKx & ~1) | Arg1 with nothing masking Arg1, so 3 also sets the enable bit again on the way down, as you say. I changed the int3472 discrete module to pass 0 when the SSDB asks for 24 MHz and 1 otherwise, so the two 19.2 MHz cameras get what they get today, and swapped it in at runtime (the _DSM runs on every clock prepare). With the previous driver at 600 MHz, the infrared sensor goes from 57.60 fps to 72.00 fps, which is 57.60 times five fourths, and back to 57.60 with the unmodified module loaded again. So 0 gives 24 MHz here, and 1 and 3 both give 19.2 MHz. So the value depends on the generation: 3 where CLKF takes two bits, as on the Surface Pro 11, and 0 on Alder Lake, where coreboot's Tiger Lake and Alder Lake camera_clock_ctl.asl document bit 0 as "0: 24MHz, 1: 19.2MHz". v3 would need to pick it per platform. I can test it on the Surface Pro 9, and I will run your driver at 396 MHz with it then. Fernando