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Mon, 26 Oct 2026 13:03:07 +0000 From: Juergen Gross To: linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Cc: Juergen Gross , Olivia Mackall , Herbert Xu Subject: [PATCH v5 07/12] hw_random/via-rng: Stop using 32-bit MSR interfaces Date: Mon, 26 Oct 2026 14:02:18 +0100 Message-ID: <20261026130223.773129-8-jgross@suse.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261026130223.773129-1-jgross@suse.com> References: <20261026130223.773129-1-jgross@suse.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Flag: NO X-Spam-Level: X-Spamd-Result: default: False [-15.80 / 50.00]; SUSE_INTERNAL_BYPASS(-9.00)[]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.996]; MIME_GOOD(-0.10)[text/plain]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; TO_DN_SOME(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email]; FROM_EQ_ENVFROM(0.00)[]; RCPT_COUNT_FIVE(0.00)[5]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Score: -15.80 The 32-bit MSR interfaces rdmsr() and wrmsr() are planned to be removed. Use the related 64-bit variants instead. Signed-off-by: Juergen Gross --- drivers/char/hw_random/via-rng.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/drivers/char/hw_random/via-rng.c b/drivers/char/hw_random/via-rng.c index a9a0a3b09c8b..b718e78d3c1c 100644 --- a/drivers/char/hw_random/via-rng.c +++ b/drivers/char/hw_random/via-rng.c @@ -129,7 +129,8 @@ static int via_rng_data_read(struct hwrng *rng, u32 *data) static int via_rng_init(struct hwrng *rng) { struct cpuinfo_x86 *c = &cpu_data(0); - u32 lo, hi, old_lo; + u32 old_lo; + struct msr val; /* VIA Nano CPUs don't have the MSR_VIA_RNG anymore. The RNG * is always enabled if CPUID rng_en is set. There is no @@ -150,32 +151,32 @@ static int via_rng_init(struct hwrng *rng) * does not say to write them as zero, so I make a guess that * we restore the values we find in the register. */ - rdmsr(MSR_VIA_RNG, lo, hi); + rdmsrq(MSR_VIA_RNG, val.q); - old_lo = lo; - lo &= ~(0x7f << VIA_STRFILT_CNT_SHIFT); - lo &= ~VIA_XSTORE_CNT_MASK; - lo &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE); - lo |= VIA_RNG_ENABLE; - lo |= VIA_NOISESRC1; + old_lo = val.l; + val.l &= ~(0x7f << VIA_STRFILT_CNT_SHIFT); + val.l &= ~VIA_XSTORE_CNT_MASK; + val.l &= ~(VIA_STRFILT_ENABLE | VIA_STRFILT_FAIL | VIA_RAWBITS_ENABLE); + val.l |= VIA_RNG_ENABLE; + val.l |= VIA_NOISESRC1; /* Enable secondary noise source on CPUs where it is present. */ /* Nehemiah stepping 8 and higher */ if ((c->x86_model == 9) && (c->x86_stepping > 7)) - lo |= VIA_NOISESRC2; + val.l |= VIA_NOISESRC2; /* Esther */ if (c->x86_model >= 10) - lo |= VIA_NOISESRC2; + val.l |= VIA_NOISESRC2; - if (lo != old_lo) - wrmsr(MSR_VIA_RNG, lo, hi); + if (val.l != old_lo) + wrmsrq(MSR_VIA_RNG, val.q); /* perhaps-unnecessary sanity check; remove after testing if unneeded */ - rdmsr(MSR_VIA_RNG, lo, hi); - if ((lo & VIA_RNG_ENABLE) == 0) { + rdmsrq(MSR_VIA_RNG, val.q); + if ((val.l & VIA_RNG_ENABLE) == 0) { pr_err(PFX "cannot enable VIA C3 RNG, aborting\n"); return -ENODEV; } -- 2.56.0