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Nikolaus Schaller" , Thomas Bogendoerfer , Paul Cercueil , Paul Burton , "Maciej W. Rozycki" Cc: oe-kbuild-all@lists.linux.dev, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, kernel@pyra-handheld.com, "H. Nikolaus Schaller" Subject: Re: [PATCH 3/6] MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2 Message-ID: <202610261320.3AF5hDGi-lkp@intel.com> References: <1658997f198411f20bc5a489e9488800e4597e19.1792956055.git.hns@goldelico.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1658997f198411f20bc5a489e9488800e4597e19.1792956055.git.hns@goldelico.com> Hi Nikolaus, kernel test robot noticed the following build errors: [auto build test ERROR on linus/master] [also build test ERROR on v7.3 next-20261023] [If your patch is applied to the wrong git tree, kindly drop us a note. And when submitting patch, we suggest to use '--base' as documented in https://git-scm.com/docs/git-format-patch#_base_tree_information] url: https://github.com/intel-lab-lkp/linux/commits/H-Nikolaus-Schaller/MIPS-Ingenic-Fix-inverted-MIPS_NO_APPENDED_DTB-logic-in-Kconfig/20261025-202050 base: linus/master patch link: https://lore.kernel.org/r/1658997f198411f20bc5a489e9488800e4597e19.1792956055.git.hns%40goldelico.com patch subject: [PATCH 3/6] MIPS: Ingenic: Add cpu-probe setup for XBurst and XBurst II R2 config: mips-allnoconfig (https://download.01.org/0day-ci/archive/20261026/202610261320.3AF5hDGi-lkp@intel.com/config) compiler: mips-linux-gcc (GCC) 16.2.0 reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261026/202610261320.3AF5hDGi-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202610261320.3AF5hDGi-lkp@intel.com/ All errors (new ones prefixed by >>): arch/mips/kernel/cpu-probe.c: In function 'cpu_probe_ingenic': >> arch/mips/kernel/cpu-probe.c:1840:30: error: 'CPU_XBURST2' undeclared (first use in this function); did you mean 'CPU_XBURST'? 1840 | c->cputype = CPU_XBURST2; | ^~~~~~~~~~~ | CPU_XBURST arch/mips/kernel/cpu-probe.c:1840:30: note: each undeclared identifier is reported only once for each function it appears in vim +1840 arch/mips/kernel/cpu-probe.c 1751 1752 static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) 1753 { 1754 decode_configs(c); 1755 1756 /* 1757 * XBurst misses a config2 register, so config3 decode was skipped in 1758 * decode_configs(). 1759 */ 1760 decode_config3(c); 1761 1762 /* XBurst does not implement the CP0 counter. */ 1763 c->options &= ~MIPS_CPU_COUNTER; 1764 BUG_ON(__builtin_constant_p(cpu_has_counter) && cpu_has_counter); 1765 1766 /* XBurst has virtually tagged icache */ 1767 c->icache.flags |= MIPS_CACHE_VTAG; 1768 1769 switch (c->processor_id & PRID_IMP_MASK) { 1770 1771 /* XBurst®1 with ISA */ 1772 case PRID_IMP_XBURST: 1773 c->cputype = CPU_XBURST; 1774 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1775 __cpu_name[cpu] = "Ingenic XBurst"; 1776 break; 1777 1778 /* XBurst®1 with MXU1.0/MXU1.1 SIMD ISA */ 1779 case PRID_IMP_XBURST_REV1: 1780 1781 /* 1782 * The XBurst core by default attempts to avoid branch target 1783 * buffer lookups by detecting & special casing loops. This 1784 * feature will cause BogoMIPS and lpj calculate in error. 1785 * Set cp0 config7 bit 4 to disable this feature. 1786 */ 1787 set_c0_config7(MIPS_CONF7_BTB_LOOP_EN); 1788 1789 switch (c->processor_id & PRID_COMP_MASK) { 1790 1791 /* 1792 * The config0 register in the XBurst CPUs with a processor ID of 1793 * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible, 1794 * but they don't actually support this ISA. 1795 */ 1796 case PRID_COMP_INGENIC_D0: 1797 c->isa_level &= ~MIPS_CPU_ISA_M32R2; 1798 1799 /* FPU is not properly detected on JZ4760(B). */ 1800 if (c->processor_id == 0x2ed0024f) 1801 c->options |= MIPS_CPU_FPU; 1802 1803 fallthrough; 1804 1805 /* 1806 * The config0 register in the XBurst CPUs with a processor ID of 1807 * PRID_COMP_INGENIC_D0 or PRID_COMP_INGENIC_D1 has an abandoned 1808 * huge page tlb mode, this mode is not compatible with the MIPS 1809 * standard, it will cause tlbmiss and into an infinite loop 1810 * (line 21 in the tlb-funcs.S) when starting the init process. 1811 * After chip reset, the default is HPTLB mode, Write 0xa9000000 1812 * to cp0 register 5 sel 4 to switch back to VTLB mode to prevent 1813 * getting stuck. 1814 */ 1815 case PRID_COMP_INGENIC_D1: 1816 write_c0_page_ctrl(XBURST_PAGECTRL_HPTLB_DIS); 1817 break; 1818 1819 default: 1820 break; 1821 } 1822 fallthrough; 1823 1824 /* XBurst®1 with MXU2.0 SIMD ISA */ 1825 case PRID_IMP_XBURST_REV2: 1826 /* Ingenic uses the WA bit to achieve write-combine memory writes */ 1827 c->writecombine = _CACHE_CACHABLE_WA; 1828 c->cputype = CPU_XBURST; 1829 __cpu_name[cpu] = "Ingenic XBurst"; 1830 break; 1831 1832 /* XBurst®2 with MXU2.1 SIMD ISA */ 1833 case PRID_IMP_XBURST2: 1834 c->cputype = CPU_XBURST; 1835 __cpu_name[cpu] = "Ingenic XBurst II"; 1836 break; 1837 1838 /* XBurst®2 with MXU3.0 SIMD ISA */ 1839 case PRID_IMP_XBURST2_R2: > 1840 c->cputype = CPU_XBURST2; 1841 c->writecombine = _CACHE_UNCACHED_ACCELERATED; 1842 __cpu_name[cpu] = "Ingenic XBurst II R2"; 1843 break; 1844 1845 default: 1846 panic("Unknown Ingenic Processor ID!"); 1847 break; 1848 } 1849 } 1850 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki