[PATCH 5/5] bpf, mips: Follow the boot-time R10000 LL/SC choice

[Imre Kaloz <kaloz@kernel.org>]

Programs are JITed after the R10000 LL/SC workaround has been selected
at boot. Emit the branch-likely in the atomic and cmpxchg ll/sc loops
only when the workaround is in use.

Signed-off-by: Imre Kaloz <kaloz@kernel.org>
---
 arch/mips/net/bpf_jit_comp.c   |  5 +++--
 arch/mips/net/bpf_jit_comp.h   | 12 +++++++-----
 arch/mips/net/bpf_jit_comp32.c |  1 +
 arch/mips/net/bpf_jit_comp64.c |  5 +++--
 4 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/arch/mips/net/bpf_jit_comp.c b/arch/mips/net/bpf_jit_comp.c
index 6ee4abe6a1f7..11e50193e205 100644
--- a/arch/mips/net/bpf_jit_comp.c
+++ b/arch/mips/net/bpf_jit_comp.c
@@ -112,6 +112,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cpu-features.h>
 #include <asm/isa-rev.h>
+#include <asm/r10k-llsc.h>
 #include <asm/uasm.h>
 
 #include "bpf_jit_comp.h"
@@ -432,7 +433,7 @@ void emit_atomic_r(struct jit_context *ctx, u8 dst, u8 src, s16 off, u8 code)
 		break;
 	}
 	emit(ctx, sc, MIPS_R_T8, off, dst);
-	emit(ctx, LLSC_beqz, MIPS_R_T8, -16 - LLSC_offset);
+	emit_llsc_beqz(ctx, MIPS_R_T8, -16 - LLSC_offset);
 	emit(ctx, nop); /* Delay slot */
 
 	if (code & BPF_FETCH) {
@@ -449,7 +450,7 @@ void emit_cmpxchg_r(struct jit_context *ctx, u8 dst, u8 src, u8 res, s16 off)
 	emit(ctx, bne, MIPS_R_T9, res, 12);
 	emit(ctx, move, MIPS_R_T8, src);     /* Delay slot */
 	emit(ctx, sc, MIPS_R_T8, off, dst);
-	emit(ctx, LLSC_beqz, MIPS_R_T8, -20 - LLSC_offset);
+	emit_llsc_beqz(ctx, MIPS_R_T8, -20 - LLSC_offset);
 	emit(ctx, move, res, MIPS_R_T9);     /* Delay slot */
 	clobber_reg(ctx, res);
 }
diff --git a/arch/mips/net/bpf_jit_comp.h b/arch/mips/net/bpf_jit_comp.h
index a37fe20818eb..3129691bccde 100644
--- a/arch/mips/net/bpf_jit_comp.h
+++ b/arch/mips/net/bpf_jit_comp.h
@@ -98,11 +98,13 @@ do {								\
 #define emit(...) __emit(__VA_ARGS__)
 
 /* Workaround for R10000 ll/sc errata */
-#ifdef CONFIG_WAR_R10000_LLSC
-#define LLSC_beqz	beqzl
-#else
-#define LLSC_beqz	beqz
-#endif
+static inline void emit_llsc_beqz(struct jit_context *ctx, u8 rs, s16 off)
+{
+	if (r10k_llsc_war)
+		emit(ctx, beqzl, rs, off);
+	else
+		emit(ctx, beqz, rs, off);
+}
 
 /* Workaround for Loongson-3 ll/sc errata */
 #ifdef CONFIG_CPU_LOONGSON3_WORKAROUNDS
diff --git a/arch/mips/net/bpf_jit_comp32.c b/arch/mips/net/bpf_jit_comp32.c
index 15a2a153dc87..07aece9edc8e 100644
--- a/arch/mips/net/bpf_jit_comp32.c
+++ b/arch/mips/net/bpf_jit_comp32.c
@@ -18,6 +18,7 @@
 #include <linux/bpf.h>
 #include <asm/cpu-features.h>
 #include <asm/isa-rev.h>
+#include <asm/r10k-llsc.h>
 #include <asm/uasm.h>
 
 #include "bpf_jit_comp.h"
diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c
index 6681ccac9dd9..fd10c8b0ece8 100644
--- a/arch/mips/net/bpf_jit_comp64.c
+++ b/arch/mips/net/bpf_jit_comp64.c
@@ -17,6 +17,7 @@
 #include <linux/bpf.h>
 #include <asm/cpu-features.h>
 #include <asm/isa-rev.h>
+#include <asm/r10k-llsc.h>
 #include <asm/uasm.h>
 
 #include "bpf_jit_comp.h"
@@ -407,7 +408,7 @@ static void emit_atomic_r64(struct jit_context *ctx,
 		break;
 	}
 	emit(ctx, scd, t2, off, dst);
-	emit(ctx, LLSC_beqz, t2, -16 - LLSC_offset);
+	emit_llsc_beqz(ctx, t2, -16 - LLSC_offset);
 	emit(ctx, nop); /* Delay slot */
 
 	if (code & BPF_FETCH) {
@@ -428,7 +429,7 @@ static void emit_cmpxchg_r64(struct jit_context *ctx, u8 dst, u8 src, s16 off)
 	emit(ctx, bne, t1, r0, 12);
 	emit(ctx, move, t2, src);      /* Delay slot */
 	emit(ctx, scd, t2, off, dst);
-	emit(ctx, LLSC_beqz, t2, -20 - LLSC_offset);
+	emit_llsc_beqz(ctx, t2, -20 - LLSC_offset);
 	emit(ctx, move, r0, t1);       /* Delay slot */
 
 	clobber_reg(ctx, r0);
-- 
2.47.3