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Peter Anvin" , Tony Luck , Reinette Chatre , Dave Martin , James Morse , Babu Moger Subject: [PATCH v3 1/5] x86/msr: Switch users of native_wrmsr() to native_wrmsrq() Date: Mon, 26 Oct 2026 15:11:16 +0100 Message-ID: <20261026141120.780172-2-jgross@suse.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261026141120.780172-1-jgross@suse.com> References: <20261026141120.780172-1-jgross@suse.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Flag: NO X-Spam-Level: X-Spamd-Result: default: False [-15.80 / 50.00]; SUSE_INTERNAL_BYPASS(-9.00)[]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.996]; MIME_GOOD(-0.10)[text/plain]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; RCPT_COUNT_TWELVE(0.00)[13]; RCVD_COUNT_TWO(0.00)[2]; RCVD_VIA_SMTP_AUTH(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[imap1.dmz-prg2.suse.org:helo,suse.com:email]; FROM_EQ_ENVFROM(0.00)[]; TO_DN_SOME(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_ALL(0.00)[] X-Spam-Score: -15.80 Switch all users of native_wrmsr() to native_wrmsrq() in order to prepare removal of native_wrmsr(). Signed-off-by: Juergen Gross --- V2: - switch order of hi and lo parts when oring them (Reinette Chatre) V3: - fix another lo | hi instance (Reinette Chatre) --- arch/x86/coco/sev/internal.h | 7 +------ arch/x86/kernel/cpu/resctrl/pseudo_lock.c | 4 ++-- 2 files changed, 3 insertions(+), 8 deletions(-) diff --git a/arch/x86/coco/sev/internal.h b/arch/x86/coco/sev/internal.h index b9632c0fc391..2e2ff48a7aae 100644 --- a/arch/x86/coco/sev/internal.h +++ b/arch/x86/coco/sev/internal.h @@ -80,12 +80,7 @@ static inline u64 sev_es_rd_ghcb_msr(void) static __always_inline void sev_es_wr_ghcb_msr(u64 val) { - u32 low, high; - - low = (u32)(val); - high = (u32)(val >> 32); - - native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high); + native_wrmsrq(MSR_AMD64_SEV_ES_GHCB, val); } enum es_result __vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt, bool write); diff --git a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c index 0408ac7f66fd..24ded41652e3 100644 --- a/arch/x86/kernel/cpu/resctrl/pseudo_lock.c +++ b/arch/x86/kernel/cpu/resctrl/pseudo_lock.c @@ -175,7 +175,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr) * pseudo-locked followed by reading of kernel memory to load it * into the cache. */ - native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, plr->closid); + native_wrmsrq(MSR_IA32_PQR_ASSOC, ((u64)plr->closid << 32) | rmid_p); /* * Cache was flushed earlier. Now access kernel memory to read it @@ -212,7 +212,7 @@ int resctrl_arch_pseudo_lock_fn(void *_plr) * Critical section end: restore closid with capacity bitmask that * does not overlap with pseudo-locked region. */ - native_wrmsr(MSR_IA32_PQR_ASSOC, rmid_p, closid_p); + native_wrmsrq(MSR_IA32_PQR_ASSOC, (u64)closid_p << 32 | rmid_p); /* Re-enable the hardware prefetcher(s) */ wrmsrq(MSR_MISC_FEATURE_CONTROL, saved_msr); -- 2.56.0