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Peter Anvin" Subject: [PATCH v3 3/5] x86/msr: Switch users of native_rdmsr() to native_rdmsrq() Date: Mon, 26 Oct 2026 15:11:18 +0100 Message-ID: <20261026141120.780172-4-jgross@suse.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261026141120.780172-1-jgross@suse.com> References: <20261026141120.780172-1-jgross@suse.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spamd-Result: default: False [-15.80 / 50.00]; SUSE_INTERNAL_BYPASS(-9.00)[]; REPLY(-4.00)[]; BAYES_HAM(-3.00)[100.00%]; MID_CONTAINS_FROM(1.00)[]; NEURAL_HAM_LONG(-1.00)[-1.000]; R_MISSING_CHARSET(0.50)[]; NEURAL_HAM_SHORT(-0.20)[-0.996]; MIME_GOOD(-0.10)[text/plain]; ARC_NA(0.00)[]; MIME_TRACE(0.00)[0:+]; RCVD_VIA_SMTP_AUTH(0.00)[]; RCPT_COUNT_SEVEN(0.00)[8]; DKIM_SIGNED(0.00)[suse.com:s=susede1]; RCVD_COUNT_TWO(0.00)[2]; FROM_HAS_DN(0.00)[]; TO_DN_SOME(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; DBL_BLOCKED_OPENRESOLVER(0.00)[suse.com:email,imap1.dmz-prg2.suse.org:helo]; RCVD_TLS_ALL(0.00)[] X-Spam-Score: -15.80 X-Spam-Level: X-Spam-Flag: NO Switch all users of native_rdmsr() to native_rdmsrq() in order to prepare removal of native_rdmsr(). Signed-off-by: Juergen Gross --- arch/x86/include/asm/microcode.h | 6 +----- arch/x86/kernel/cpu/intel.c | 6 +++--- arch/x86/kernel/cpu/microcode/amd.c | 4 ++-- arch/x86/kernel/cpu/microcode/core.c | 4 ++-- 4 files changed, 8 insertions(+), 12 deletions(-) diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h index 645e65ac1586..6eef329def4b 100644 --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -64,17 +64,13 @@ static inline int intel_microcode_get_datasize(struct microcode_header_intel *hd static inline u32 intel_get_microcode_revision(void) { - u32 rev, dummy; - native_wrmsrq(MSR_IA32_UCODE_REV, 0); /* As documented in the SDM: Do a CPUID 1 here */ native_cpuid_eax(1); /* get the current revision from MSR 0x8B */ - native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev); - - return rev; + return native_rdmsrq(MSR_IA32_UCODE_REV) >> 32; } #endif /* !CONFIG_CPU_SUP_INTEL */ diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 2aabe9affa0c..99474f160b86 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -214,7 +214,7 @@ static u32 intel_cpuid_vfm(void) u32 intel_get_platform_id(void) { - unsigned int val[2]; + u64 val; if (x86_hypervisor_present) return 0; @@ -229,9 +229,9 @@ u32 intel_get_platform_id(void) return 0; /* get processor flags from MSR 0x17 */ - native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); + val = native_rdmsrq(MSR_IA32_PLATFORM_ID); - return (val[1] >> 18) & 7; + return (val >> 50) & 7; } static void early_init_intel(struct cpuinfo_x86 *c) diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index 6cdc410e7547..f6dc79dd18dd 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -315,7 +315,7 @@ static union cpuid_1_eax ucode_rev_to_cpuid(unsigned int val) static u32 get_patch_level(void) { - u32 rev, dummy __always_unused; + u32 rev; if (IS_ENABLED(CONFIG_MICROCODE_DBG) && x86_hypervisor_present) { int cpu = smp_processor_id(); @@ -332,7 +332,7 @@ static u32 get_patch_level(void) return microcode_rev[cpu]; } - native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy); + rev = native_rdmsrq(MSR_AMD64_PATCH_LEVEL); if (!rev) { if (x86_family(bsp_cpuid_1_eax) < 0x17) return rev; diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index 0dd0c7241c57..ea696a202c31 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -94,13 +94,13 @@ struct early_load_data early_data; */ static bool amd_check_current_patch_level(void) { - u32 lvl, dummy, i; + u32 lvl, i; u32 *levels; if (x86_cpuid_vendor() != X86_VENDOR_AMD) return false; - native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); + lvl = native_rdmsrq(MSR_AMD64_PATCH_LEVEL); levels = final_levels; -- 2.56.0