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Tue, 27 Oct 2026 04:19:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1793074769; bh=+BV2XxKdkCDmCph23X+rU19KYGP6JPt3AiobjVr4wX4=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To; b=Gsl3ngS3zAqSzI9fyfyI2yr75xroiTqgGdH6xPP6To+f56VKQ3uxk1zY84eGzk0+b UAp3Sr19UOj9113tw5Yct+rpSp29EHDKrNgM4vxRXp1ny9153P+jU7m1L37lHK+Ps5 ak3CfFKIYcURXAuhBGBrl0+hQMFPlMpJ+7cSFBGDFBwWsy26L4y/4az6Xmf7HwzRPx 7FNAJOR/8aSgv7MY9DdWmGfMbUaEVCTulk55cdNfnMhttjQw2y1f82weGDL1pN8zkQ nSAFreF1oMDtKMzFdibscREoeRGNZfAbgDvjP5unnXqnkM6z66ofv3WZgML/h/OgEg b6aGYcpEFLjOg== Received: from nexus.subspace.kernel.org (localhost [IPv6:::1]) by lkml.kernel.org (Postfix) with ESMTP id D7AC044F94; Tue, 27 Oct 2026 04:19:26 +0000 (UTC) From: Long Zhao via B4 Relay Date: Tue, 27 Oct 2026 12:18:53 +0800 Subject: [PATCH v12 06/11] gpio: pl061: use cleanup helpers for locks X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Message-Id: <20261027-cv75-gpio-v12-6-c22555400e18@ambarella.com> References: <20261027-cv75-gpio-v12-0-c22555400e18@ambarella.com> In-Reply-To: <20261027-cv75-gpio-v12-0-c22555400e18@ambarella.com> To: Bartosz Golaszewski , linux-gpio@vger.kernel.org Cc: Linus Walleij , Michael Walle , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Krzysztof Kozlowski , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org, Long Zhao , Long Zhao , linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793074764; l=3548; i=longzhao@ambarella.com; s=20260730; h=from:subject:message-id; bh=e5A/nNp2mkLE1rfoTrTjsYU6GxM1J3kjTE+rcuksRMg=; b=mcPLOijAXlO+UG5Vo9BosWoQv2BAIGeOaVK4NJSF5CVseFqRZbk0ChSd4w4+thz6Z4ukXPPsZ FbeQScbF57OBcA2tqyQcw1hjm9SJpCPVIUmAMIi3L8RMBkz4D6OsARA X-Developer-Key: i=longzhao@ambarella.com; a=ed25519; pk=/xGhPTOX0/eYsyTWzyjjgAIW1Z/YD+IlnOnvcdRozow= X-Endpoint-Received: by B4 Relay for longzhao@ambarella.com/20260730 with auth_id=903 X-Original-From: Long Zhao Reply-To: longzhao@ambarella.com Content-Transfer-Encoding: 7bit From: Long Zhao Convert raw_spinlock critical sections to guard()() from cleanup.h. Reviewed-by: Linus Walleij Reviewed-by: Andy Shevchenko Signed-off-by: Long Zhao --- drivers/gpio/gpio-pl061.c | 27 ++++++++++----------------- 1 file changed, 10 insertions(+), 17 deletions(-) diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c index e0ac8335bae4..a232b63fbc0b 100644 --- a/drivers/gpio/gpio-pl061.c +++ b/drivers/gpio/gpio-pl061.c @@ -10,6 +10,7 @@ */ #include #include +#include #include #include #include @@ -105,11 +106,10 @@ static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) { struct pl061 *pl061 = gpiochip_get_data(gc); - unsigned long flags; - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); + regmap_clear_bits(pl061->regmap, GPIODIR, BIT(offset)); - raw_spin_unlock_irqrestore(&pl061->lock, flags); return 0; } @@ -119,9 +119,9 @@ static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, { struct pl061 *pl061 = gpiochip_get_data(gc); unsigned int mask = BIT(offset); - unsigned long flags; - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); + regmap_assign_bits(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), BIT(offset), value); regmap_set_bits(pl061->regmap, GPIODIR, mask); @@ -132,7 +132,6 @@ static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, */ regmap_assign_bits(pl061->regmap, BIT(offset + PL061_DATA_OFFSET), BIT(offset), value); - raw_spin_unlock_irqrestore(&pl061->lock, flags); return 0; } @@ -162,7 +161,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger) unsigned int gpioiev = 0; unsigned int gpioibe = 0; unsigned int gpiois = 0; - unsigned long flags; if (offset < 0 || offset >= PL061_GPIO_NR) return -EINVAL; @@ -175,8 +173,7 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger) return -EINVAL; } - - raw_spin_lock_irqsave(&pl061->lock, flags); + guard(raw_spinlock_irqsave)(&pl061->lock); regmap_read(pl061->regmap, GPIOIEV, &gpioiev); regmap_read(pl061->regmap, GPIOIS, &gpiois); @@ -236,8 +233,6 @@ static int pl061_irq_type(struct irq_data *d, unsigned trigger) regmap_write(pl061->regmap, GPIOIBE, gpioibe); regmap_write(pl061->regmap, GPIOIEV, gpioiev); - raw_spin_unlock_irqrestore(&pl061->lock, flags); - return 0; } @@ -266,9 +261,8 @@ static void pl061_irq_mask(struct irq_data *d) struct pl061 *pl061 = gpiochip_get_data(gc); u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); - raw_spin_lock(&pl061->lock); - regmap_clear_bits(pl061->regmap, GPIOIE, mask); - raw_spin_unlock(&pl061->lock); + scoped_guard(raw_spinlock, &pl061->lock) + regmap_clear_bits(pl061->regmap, GPIOIE, mask); gpiochip_disable_irq(gc, d->hwirq); } @@ -281,9 +275,8 @@ static void pl061_irq_unmask(struct irq_data *d) gpiochip_enable_irq(gc, d->hwirq); - raw_spin_lock(&pl061->lock); - regmap_set_bits(pl061->regmap, GPIOIE, mask); - raw_spin_unlock(&pl061->lock); + scoped_guard(raw_spinlock, &pl061->lock) + regmap_set_bits(pl061->regmap, GPIOIE, mask); } /** -- 2.34.1