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Tue, 27 Oct 2026 11:08:36 -0700 (PDT) Received: from hu-tdas-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-198a0d98660sm39144463c88.9.2026.10.27.11.08.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 11:08:35 -0700 (PDT) From: Taniya Das Subject: [PATCH v3 0/4] clk: qcom: Add Nord DPRX clock controller support Date: Tue, 27 Oct 2026 23:38:25 +0530 Message-Id: <20261027-nords_dprx-v3-0-5d98b2c6c263@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAJno4GoC/23MywrCMBCF4VcpWZuSG0115XuISMzFBmxTMxoqJ e9uWhAquBn4B843I7DRW0CHakbRJg8+DCX4rkK6U8PNYm9KI0ZYQ/aE4yFEAxczxgmL0kYqrVt BURmM0To/rdjpXLrz8AzxvdqJLt8vI7dMophgIyRTjjtCr/QYAOrHS9116Pu6HLRoiW0EJn4EV gSnBG+EJa207o+Qc/4ArZ2sUu0AAAA= X-Change-ID: 20260903-nords_dprx-4903d7acc841 To: Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Abel Vesa , Satya Priya Kakitapalli , Vladimir Zapolskiy Cc: Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Taniya Das , stable@vger.kernel.org, Konrad Dybcio , Abel Vesa , Krzysztof Kozlowski X-Mailer: b4 0.15-dev-aa3f6 X-Authority-Analysis: v=2.4 cv=GYyCDgXL c=1 sm=1 tr=0 ts=6ae0e8a7 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=dhWb7Yg5Oiobcms0P14A:9 a=QEXdDO2ut3YA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-ORIG-GUID: 7LSI1xMcpT-DJCXvbCLhmpEE4tyFHPo3 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI3MDA3MiBTYWx0ZWRfXxTcXKZ3krklo JtrarJYZYnVN0NBI0SWdydkisSOMv8MkIYBQaj1cCZvPEsvpXywd+3Yw6kWKbPeNASsqegciyJ4 xkrA9pIPVhrV1aG4ghDP8CLGXecKWVOXmb9XbFN6lcknPqGm2rGYsJhk5FVVTwqKaojSVTkwh/B +WfVB/9f1NKRAU90xpxjU0y3Gqhq87zbZNod70DfiPwBhOibr25ksV2/ZMox7EpliG8kOYyVx3E 6SlkdJ79dpCdapie+WxxhuYYuObDFeLofi6yJPGvVjsr01OLStWHjQ9Di37YhI7nX9fXupIbaF6 nz1jdAyx0qsqCOQduXT6/4J0ZFzsIlE+/TxrhusA5hEA2g8APh77B9pUwhcSiArTnN3Z9VikKY4 JdIVg8nbZxe8ys1Zg0emN7iF7LKYxqEgNqe5lxQAtifYE89tvMO2XNEGS//49rW31NolJw9P8JJ nlOgGBGwxwaTs47RCPA== X-Proofpoint-GUID: 7LSI1xMcpT-DJCXvbCLhmpEE4tyFHPo3 X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI3MDA3MiBTYWx0ZWRfX38IxjXUYrfAQ /fCGOs1wgsmGjsX7XS124+y/plW6KOlTu1T/uzAVxCV+eLttz4Yqpv7QA2J/UI95ysu5T8mfeXl o1CLtKtV3l5yX4OraUE+06PfP9qhBp4= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-27_04,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 malwarescore=0 impostorscore=0 phishscore=0 clxscore=1015 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610270072 Add support for the DisplayPort Receiver (DPRX) clock controllers found on Qualcomm Nord devices. There are two identical DPRX clock controller instances (DPRX0 and DPRX1), each providing clocks for the DPRX core, audio, AHB and video memory paths, along with their core PLLs. The DPRX PLLs are ZONDA_OLE instances whose PLL_ALPHA_VAL register has been widened to 28 bits to carry the fractional word at a finer resolution. The alpha-PLL core must support that width for the DPRX PLLs to lock to and report the correct rate. The series is organized as follows: - Patch 1 fixes Zonda PLL L-value rounding. - Patch 2 adds alpha-PLL support for a 28-bit ALPHA_VAL width. - Patch 3 documents the Nord DPRX clock controller DT bindings. - Patch 4 adds the two DPRX clock controller drivers. Changes in v3: - Add a separate fix for Zonda PLL L-value rounding. - Add runtime PM support and use masked divider register updates. - Use the preferred items form for the power-domains binding property. - Link to v2: https://lore.kernel.org/r/20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com Changes in v2: - Address review comments: remove unused definitions and includes, rewrap the alpha-width ternary, and clarify that DPRXCC provides clocks and resets. - Add RB-by tag [Abel] - Link to v1: https://lore.kernel.org/r/20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com Signed-off-by: Taniya Das --- Taniya Das (4): clk: qcom: clk-alpha-pll: fix Zonda L value rounding clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width dt-bindings: clock: qcom: document the Nord DPRX Clock Controller clk: qcom: dprxcc: Add Nord DPRX clock controller support .../bindings/clock/qcom,nord-dprxcc.yaml | 67 ++++ drivers/clk/qcom/Kconfig | 11 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-alpha-pll.c | 10 +- drivers/clk/qcom/clk-alpha-pll.h | 3 + drivers/clk/qcom/dprxcc0-nord.c | 441 +++++++++++++++++++++ drivers/clk/qcom/dprxcc1-nord.c | 440 ++++++++++++++++++++ include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 ++ 8 files changed, 995 insertions(+), 5 deletions(-) --- base-commit: f1ac44c32cba88ad65dcecd4a279661d14e93651 change-id: 20260903-nords_dprx-4903d7acc841 Best regards, -- Taniya Das