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The alpha-PLL core, however, derives the ALPHA_VAL width solely from the register-map layout and can only express 16 or 40 bits, so it programs and reads back the 28-bit configuration at the wrong scale on both the set_rate/slew and recalc_rate paths, making the PLL lock to and report the wrong rate. Add a way to identify the wider register: an optional alpha_width field in struct clk_alpha_pll that, when non-zero, supersedes the register-derived width. This feeds pll_alpha_width(), so the recalc_rate and round_rate math scale the fractional word correctly, and the Zonda set_rate L-adjust MSB check is derived from the active width instead of a hardcoded BIT(15). PLLs that leave the field zero retain the previous behaviour. Reviewed-by: Abel Vesa Acked-by: Konrad Dybcio Reviewed-by: Shawn Guo Signed-off-by: Taniya Das --- drivers/clk/qcom/clk-alpha-pll.c | 8 ++++---- drivers/clk/qcom/clk-alpha-pll.h | 3 +++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 9782fb062a58a26daf3e911ad23c5e1d805b0c38..9726e6ea7f5f80a6355aa58c345657aad8c157c0 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -41,7 +41,6 @@ #define PLL_USER_CTL(p) ((p)->offset + (p)->regs[PLL_OFF_USER_CTL]) # define PLL_POST_DIV_SHIFT 8 # define PLL_POST_DIV_MASK(p) GENMASK((p)->width ? (p)->width - 1 : 3, 0) -# define PLL_ALPHA_MSB BIT(15) # define PLL_ALPHA_EN BIT(24) # define PLL_ALPHA_MODE BIT(25) # define PLL_VCO_SHIFT 20 @@ -382,8 +381,9 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs); #define ZONDA_PLL_FREQ_LOCK_DET BIT(29) #define pll_alpha_width(p) \ - ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ - ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH) + ((p)->alpha_width ? (p)->alpha_width : \ + ((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ? \ + ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)) #define pll_has_64bit_config(p) ((PLL_CONFIG_CTL_U(p) - PLL_CONFIG_CTL(p)) == 4) @@ -2290,7 +2290,7 @@ static int clk_zonda_pll_set_rate(struct clk_hw *hw, unsigned long rate, if (ret < 0) return ret; - if (a & PLL_ALPHA_MSB) + if (a & BIT(alpha_width - 1)) zonda_pll_adjust_l_val(rate, prate, &l); regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a); diff --git a/drivers/clk/qcom/clk-alpha-pll.h b/drivers/clk/qcom/clk-alpha-pll.h index 3a2157bebc52cd15f55381a068953f21be18f6bb..ab3b4f4fc7501df0fa3f59d741d64646383e4cfd 100644 --- a/drivers/clk/qcom/clk-alpha-pll.h +++ b/drivers/clk/qcom/clk-alpha-pll.h @@ -86,6 +86,8 @@ struct pll_vco { * struct clk_alpha_pll - phase locked loop (PLL) * @offset: base address of registers * @regs: alpha pll register map (see @clk_alpha_pll_regs) + * @alpha_width: optional override of the ALPHA_VAL width in bits; + * 0 means derive the width from @regs * @config: array of pll settings * @vco_table: array of VCO settings * @num_vco: number of VCO settings in @vco_table @@ -95,6 +97,7 @@ struct pll_vco { struct clk_alpha_pll { u32 offset; const u8 *regs; + u32 alpha_width; const struct alpha_pll_config *config; const struct pll_vco *vco_table; -- 2.34.1