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[174.29.1.49]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-850fb0741c9sm12093328a34.10.2026.10.27.16.05.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 16:05:42 -0700 (PDT) From: James Hilliard Subject: [PATCH v4 0/5] serial: 8250_dw: describe the Allwinner H616 UART configuration Date: Tue, 27 Oct 2026 17:05:28 -0600 Message-Id: <20261027-submit-h616-uart-fifo-v1-v4-0-d37e018fd0a6@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/42R3U7DMAyFX6XqNUb5T5kQ4j3QLpzU2YLWFZKuD E17d9JuExNiCCk3VuzvHPsc6kwpUq4X1aFONMYc+20p1F1V+zVuVwSxLXUtmDCcCQF557o4wNp wAztMA4QYehg5eI3Bt4G0d6wu42+JQtzP6JflqS6zr+SHiTd1rGMe+vQ5a4986rvIyNsy5TEgh dIhCXLYPK86jJt733f1JDOK/4JEAWFg+kFqpozUP0HyGqT+AMkCEo0JnrvGS8+vQcfT5oned+W 2w+kctcNMUP4LcFEZp5xWMiBvrLbiwaK32qAJZMiooJlxtlEKp5N1lDPOoSyqx7M1e7E2RYkba IRm0H5AG0ucfZotKuCguOUKrSau8dvi0y2s+g2b9kOKK9jEQEPs6BwIByt5MdlqxmR7zV4ej1/ X+joJYwIAAA== X-Change-ID: 20261022-submit-h616-uart-fifo-v1-c5afcdfe5cb0 To: Greg Kroah-Hartman , Jiri Slaby , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, James Hilliard X-Mailer: b4 0.15.2 H616 has 256-byte UART FIFOs, but lacks the DesignWare component parameter register used to discover their capacity. Its debug-divisor and RS485 registers also overlap offsets used to probe optional DesignWare features. Add an H616 compatible for the integration-specific setup. Keep the existing 16550A port type and describe its fixed FIFO depth in platform data. Use common Allwinner helpers to configure the transmit load and receive thresholds from that depth. Configure automatic flow control, preserve the BUSY-safe integer divisor path and keep the UART gate enabled during termios changes. The H616 configuration uses PIO. The series first introduces platform setup callbacks and a shared RX trigger conversion helper, then adds the binding, H616 setup and SoC DTS changes. Based on tty-next at 6b4b543fa187 with the posted RX trigger callback-lifetime fix [0] and DW BUSY-safe divisor fix v4 [1]. Platform setup runs before installing the BUSY-safe divisor setter. [0] https://lore.kernel.org/r/20261024-submit-serial-8250-rxtrig-lifetime-v1-v1-1-731b78d5003d@gmail.com [1] https://lore.kernel.org/r/20261027-submit-serial-8250-dw-divisor-v1-v4-1-41714a75e15a@gmail.com Assisted-by: Codex:gpt-6-astra Signed-off-by: James Hilliard --- Changes in v4: - Introduce common Allwinner setup helpers with the fixed FIFO depth supplied by compatible-specific platform data. - Rebase onto tty-next at 6b4b543fa187 and the posted DW divisor v4 fix, installing the BUSY-safe setter after platform setup. - Use an early return for FIFO-less DMA setup, following Andy's review. - Default to generic setup when platform data has no setup callback. - Select Octeon's optional-register discovery with IS_ENABLED() in its setup helper, preserving the existing 32-bit and 64-bit behavior. - Extract the shared 8250 bytes-to-FCR conversion, including the unsupported-table check, into a preparatory patch and use it for H616, following Andy's review. - Set the fixed 256-byte FIFO depth in H616 platform data and omit fifo-size from its binding and DTS, following Krzysztof's review. - Precompute the Allwinner RX thresholds during setup and retain the sunxi FIFO-depth helper for filling the table. Use named FCR encodings in the helper, following Jiri's review. - Share threshold-table initialization and callback assignment through a sunxi RX trigger setup helper. - Group and comment the H616 trigger and RS485 setup. - Link to v3: https://patch.msgid.link/20261024-submit-h616-uart-fifo-v1-v3-0-286fc1b8c3c1@gmail.com Changes in v3: - Introduce a platform-data setup callback in a preparatory patch, replacing skip_autocfg and preserving the existing Octeon setup. - Describe each H616 UART's FIFO capacity with the standard fifo-size DT property and use the value already read by uart_read_port_properties(). - Derive the Allwinner RX trigger thresholds from the FIFO depth. - Use an unsigned trigger index and conditional runtime PM guard, preserving error propagation when the device cannot resume. - Rebase onto tty-next, replacing the earlier DMA prerequisites with the posted RX trigger callback-lifetime fix. - Separate DMA enablement into follow-up work, retaining PIO operation for the H616 FIFO configuration. - Link to v2: https://lore.kernel.org/r/20261023-submit-h616-uart-fifo-v1-v2-0-af0593504635@gmail.com Changes in v2: - Keep PORT_16550A and set the FIFO size, transmit load and capabilities during setup, following Andy's review. - Select H616 setup through the matched platform-data pointer and remove the type and DMA burst-size platform-data members. - Use get_rxtrig/set_rxtrig for the 1/64/128/254-byte receive thresholds, with port locking and runtime PM around register updates. Keep the standard half-full FCR default, selecting 128 bytes on H616. - Advertise UART_CAP_AFE so CRTSCTS enables hardware automatic flow control. - Rebase onto next-20261023 and declare the posted sun6i pause/lifetime fixes and their prerequisites for DMA enablement. - Link to v1: https://lore.kernel.org/r/20261023-submit-h616-uart-fifo-v1-v1-0-e4a3bae2eba8@gmail.com To: Andy Shevchenko To: Ilpo Järvinen To: Greg Kroah-Hartman To: Jiri Slaby To: Rob Herring To: Krzysztof Kozlowski To: Conor Dooley To: Chen-Yu Tsai To: Jernej Skrabec To: Samuel Holland Cc: linux-kernel@vger.kernel.org Cc: linux-serial@vger.kernel.org Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-sunxi@lists.linux.dev --- James Hilliard (5): serial: 8250_dw: select port setup through platform data serial: 8250: share the RX trigger conversion helper dt-bindings: serial: snps-dw-apb-uart: add Allwinner H616 serial: 8250_dw: configure the Allwinner H616 UART arm64: dts: allwinner: h616: describe the UART integration .../bindings/serial/snps-dw-apb-uart.yaml | 1 + arch/arm64/boot/dts/allwinner/sun50i-h616.dtsi | 12 +- drivers/tty/serial/8250/8250.h | 16 +++ drivers/tty/serial/8250/8250_dw.c | 138 +++++++++++++++++++-- drivers/tty/serial/8250/8250_port.c | 12 +- 5 files changed, 151 insertions(+), 28 deletions(-) --- base-commit: 6b4b543fa18757297ac756a6fe6e64f506b7844a change-id: 20261022-submit-h616-uart-fifo-v1-c5afcdfe5cb0 prerequisite-message-id: <20261027-submit-serial-8250-dw-divisor-v1-v4-1-41714a75e15a@gmail.com> prerequisite-patch-id: d8219673210dac82d3adab41578ff2f76f5862c9 prerequisite-message-id: <20261024-submit-serial-8250-rxtrig-lifetime-v1-v1-1-731b78d5003d@gmail.com> prerequisite-patch-id: 9a9395c715c2bf7bbcae5bdd16a339d7f2af6269 Best regards, -- James Hilliard