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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-369e8d93663sm33542534eec.13.2026.10.26.18.55.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 18:55:49 -0700 (PDT) From: Peter Chen To: Vinod Koul Cc: Neil Armstrong , Manivannan Sadhasivam , Konrad Dybcio , Elson Serrao , Ronak Raheja , Wesley Cheng , Udipto Goswami , Jack Pham , Pratham Pratap , Krishna Kurapati , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org, Peter Chen Subject: [PATCH v2 1/1] phy: qualcomm: m31-eusb2: Add register XCFGI_159_152 for SE0 recovery Date: Mon, 26 Oct 2026 18:55:45 -0700 Message-ID: <20261027015545.2758784-1-peter.chen@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI3MDAwNyBTYWx0ZWRfX0GKfJ4u2xvxA 3BO6w82N/Mjc+V2bm4QWrlo4d1vEUJRfwwbfST0yqvSNQyAruR8437B+zyrKgoU5tk3KhG1pg/9 RyBQGSX7cH8IFpM5HaNdROZZtYfEW3I= X-Authority-Analysis: v=2.4 cv=ZOdCCn7b c=1 sm=1 tr=0 ts=6ae004a8 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=fkmqLtjFOitS6APqvyEA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-GUID: GfqZA-YDYcgI-VEUGxXGFc5zibnoqqcm X-Proofpoint-ORIG-GUID: GfqZA-YDYcgI-VEUGxXGFc5zibnoqqcm X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI3MDAwNyBTYWx0ZWRfX8eLYXAbDR7BI 38yKLznnmXElJCuULPA7HAUmmx8MD1IdCevxl0081jzQ3DrseHT3qQN5wx20BlQa39h65Yyt20k hWZBepDHkf6MtmOt5szLnHm9FkRC1RdGB8t1HoouUwLl0iHiN7sATqbMQqbsMoxiPrs1U3RWcDz y8z9yN2Y17+KdqqBncV9+lZ9BhuEGYE059KPvakLQCs3o6z2VOPJPfokVoOJ2iql03JIfAYOuRS oabuLLJEHDpvAOwC6nXYJIC9M8NOqbiVjM2VCg/moBkjXSqLVwek1hlq30EDjKOV4VbuJWOmGHm W6n770jjx1mZPi1nVNz24WBrBc581t0/jMJ4ovaEK3JGJ5ITvHdveZsKC3hu60yzxap6C2A5mle akPp5J4Sy5TPq8jGKMLd+3m7frxxVlgdhC7pQCVKkuGTlOgqlH+eo4ZtafANgMix1wszCJDkA0f PHCSyOe1dDNnFRZa0iw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-26_05,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 bulkscore=0 impostorscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610270007 From: Elson Serrao This patch introduces support for the XCFGI_159_152 register to enable a hardware-based SE0 recovery mechanism in the M31 PHY when operating in host mode. During PHY initialization, spurious pulses from external devices can interfere with speed negotiation, potentially leading to abnormal behavior. To mitigate this, the M31 PHY provides a fail-safe mechanism controlled by bit 159 of the XCFGI register. When XCFG_SE0_TIMEOUT_EN (bit 159) is set, a hardware counter is activated to monitor the SE0 state. If SE0 persists for more than 2.5 ms before entering L0 mode, the PHY interprets this as bus inactivity and resets the state machine to its default state. After transitioning to L0, the PHY resumes normal operation in accordance with the eUSB specification. Fixes: 9c8504861cc4 ("phy: qcom: Add M31 based eUSB2 PHY driver") Reviewed-by: Konrad Dybcio Signed-off-by: Elson Serrao Signed-off-by: Peter Chen --- Changes for v2: - Add Fixes and Reviewed-by tags - Link to v1: https://lore.kernel.org/all/20261020061811.3127511-1-peter.chen@oss.qualcomm.com/ drivers/phy/qualcomm/phy-qcom-m31-eusb2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c index 275df38256de..8d954e772585 100644 --- a/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c +++ b/drivers/phy/qualcomm/phy-qcom-m31-eusb2.c @@ -56,6 +56,9 @@ #define USB_PHY_XCFGI_7_0 (0x15c) #define PLL_LOCK_TIME GENMASK(1, 0) +#define USB_PHY_XCFGI_159_152 (0x1a8) +#define SE0_TIMEOUT_EN BIT(7) + #define M31_EUSB_PHY_INIT_CFG(o, b, v) \ { \ .off = o, \ @@ -88,6 +91,13 @@ static const struct m31_phy_tbl_entry m31_eusb2_setup_tbl[] = { }; static const struct m31_phy_tbl_entry m31_eusb_phy_override_tbl[] = { + /* + * Set XCFGI[159] to enable SE0 timeout mechanism in M31. + * This enables a counter which will assume bus inactive if + * SE0 is more than 2.5ms and reset the state machine to default + * state. + */ + M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_159_152, SE0_TIMEOUT_EN, 1), M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_39_32, HSTX_PE, 0), M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_71_64, HSTX_SWING, 7), M31_EUSB_PHY_INIT_CFG(USB_PHY_XCFGI_31_24, HSTX_SLEW, 0), -- 2.43.0