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Tue, 27 Oct 2026 00:47:22 -0700 (PDT) Received: from li-1a3e774c-28e4-11b2-a85c-acc9f2883e29.ibm.com.com ([106.51.165.23]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-198a0e8d700sm36526698c88.10.2026.10.27.00.47.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 00:47:21 -0700 (PDT) From: "Mukesh Kumar Chaurasiya (IBM)" To: maddy@linux.ibm.com, mpe@ellerman.id.au, npiggin@gmail.com, chleroy@kernel.org, ritesh.list@gmail.com, sshegde@linux.ibm.com, bigeasy@linutronix.de, clrkwllms@kernel.org, rostedt@goodmis.org, mkchauras@gmail.com, msuchanek@suse.de, bwiedemann@suse.de, ryan.roberts@arm.com, mchauras@linux.ibm.com, agordeev@linux.ibm.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-rt-devel@lists.linux.dev Subject: [PATCH V2] powerpc: Support for generic TIF bits Date: Tue, 27 Oct 2026 13:17:10 +0530 Message-ID: <20261027074710.129819-1-mkchauras@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit powerpc already uses GENERIC_ENTRY for the irq entry/exit path. That means the generic entry code handles all the arch-independent thread_info flags (TIF_SIGPENDING, TIF_NOTIFY_RESUME, TIF_NOTIFY_SIGNAL, TIF_NEED_RESCHED, TIF_NEED_RESCHED_LAZY, TIF_UPROBE, TIF_PATCH_PENDING, TIF_MEMDIE, TIF_RSEQ, TIF_HRTIMER_REARM, TIF_USER_RETURN_NOTIFY) on behalf of the arch. The only remaining blocker was that powerpc defined its own bit numbers for those flags, which conflicted with the layout required by the common header include/asm-generic/thread_info_tif.h. This patch selects HAVE_GENERIC_TIF_BITS and switches powerpc's thread_info.h over to include for the arch-independent bits, using HAVE_TIF_NEED_RESCHED_LAZY to opt in to the lazy-preemption flag. The powerpc-private bits (TIF_RESTORE_TM, TIF_SINGLESTEP, TIF_RESTOREALL, TIF_NOERROR, TIF_EMULATE_STACK_STORE, TIF_ELF2ABI, TIF_POLLING_NRFLAG, TIF_32BIT, TIF_SYSCALL_RET) are renumbered to start at bit 16, which is the reserved range for arch use. Enabling HAVE_GENERIC_TIF_BITS unlocks the following features that were previously unavailable on powerpc because their Kconfig dependencies could not be satisfied: 1. RSEQ_SLICE_EXTENSION (CONFIG_RSEQ_SLICE_EXTENSION) Allows userspace to register an RSEQ critical section and request a limited time-slice extension when the task is about to be preempted. The kernel grants the extension (via the RSEQ shared data ABI) so the critical section can complete, avoiding the thundering-herd problem where many threads spin on the same lock/resource after a preemption. This feature requires a dedicated TIF_RSEQ bit, which only exists when HAVE_GENERIC_TIF_BITS is set. Depends on: RSEQ && HIGH_RES_TIMERS && GENERIC_ENTRY && HAVE_GENERIC_TIF_BITS. 2. HRTIMER_REARM_DEFERRED (CONFIG_HRTIMER_REARM_DEFERRED) Defers re-arming of the hrtimer interrupt to the return-to-user path, using the dedicated TIF_HRTIMER_REARM bit. This avoids redundant hrtimer_interrupt() invocations within the same tick period and reduces latency jitter for high-resolution timer users (e.g., PREEMPT_RT workloads, audio, real-time tasks). Depends on: GENERIC_ENTRY && HAVE_GENERIC_TIF_BITS && HIGH_RES_TIMERS && SCHED_HRTICK. 3. Dedicated TIF_RSEQ flag (fast-path RSEQ handling) Without HAVE_GENERIC_TIF_BITS, TIF_RSEQ falls back to aliasing TIF_NOTIFY_RESUME, forcing the generic entry slow-path to run on every return-to-user for all RSEQ-registered threads. With the dedicated bit, the fast path can skip RSEQ work unless the flag is actually set, reducing overhead in the common case. 4. TIF_USER_RETURN_NOTIFY The generic bit for the user-return-notifier subsystem (kernel/user-return-notifier.c). Used by KVM on x86 to lazily restore guest MSRs; having the generic bit available means future powerpc KVM work can use the same infrastructure. The arch-specific bits that do not exist in the generic header retain their private numbering in the powerpc-reserved range (bits 16+), so no existing powerpc functionality is affected. Tested on powerpc (POWER11 pSeries CONFIG_RSEQ=y + CONFIG_RSEQ_SLICE_EXTENSION=y + CONFIG_HRTIMER_REARM_DEFERRED=y): * tools/testing/selftests/rseq/ -- all tests pass (basic_test, param_test, basic_percpu_ops_test, syscall_errors_test, slice_test via run_timeslice_test.sh) * tools/testing/selftests/timers/hrtimer-rearm.sh -- deferred=1 events observed; no new dmesg warnings * Boot and basic workload testing shows no regression Signed-off-by: Mukesh Kumar Chaurasiya (IBM) --- This patch is applicabe over https://lore.kernel.org/all/961c058f3f3e03045552186c083a68a0fde3f43f.1791975972.git.msuchanek@suse.de/ Changelog: V1 -> V2: - Commit message updated V1: https://lore.kernel.org/all/20261021144453.232372-2-mkchauras@gmail.com/ arch/powerpc/Kconfig | 1 + arch/powerpc/include/asm/thread_info.h | 36 +++++++++----------------- 2 files changed, 13 insertions(+), 24 deletions(-) diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 7f7910f38a67..e5527b56159a 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -255,6 +255,7 @@ config PPC select HAVE_FUNCTION_GRAPH_TRACER select HAVE_FUNCTION_TRACER if !COMPILE_TEST && (PPC64 || (PPC32 && CC_IS_GCC)) select HAVE_GCC_PLUGINS + select HAVE_GENERIC_TIF_BITS select HAVE_HARDLOCKUP_DETECTOR_ARCH if PPC_BOOK3S_64 && SMP select HAVE_HARDLOCKUP_DETECTOR_PERF if PERF_EVENTS && HAVE_PERF_EVENTS_NMI select HAVE_HW_BREAKPOINT if PERF_EVENTS && (PPC_BOOK3S || PPC_8xx) diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h index 4b7ec1db3034..4df3f4b5bd56 100644 --- a/arch/powerpc/include/asm/thread_info.h +++ b/arch/powerpc/include/asm/thread_info.h @@ -93,44 +93,32 @@ void arch_setup_new_exec(void); #endif /* __ASSEMBLER__ */ +#define HAVE_TIF_NEED_RESCHED_LAZY + +#include /* * thread information flag bit numbers */ -#define TIF_SIGPENDING 1 /* signal pending */ -#define TIF_NEED_RESCHED 2 /* rescheduling necessary */ -#define TIF_NOTIFY_SIGNAL 3 /* signal notifications exist */ -#define TIF_RESTORE_TM 5 /* need to restore TM FP/VEC/VSX */ -#define TIF_PATCH_PENDING 6 /* pending live patching update */ -#define TIF_SINGLESTEP 8 /* singlestepping active */ -#define TIF_NEED_RESCHED_LAZY 9 /* Scheduler driven lazy preemption */ -#define TIF_RESTOREALL 11 /* Restore all regs (implies NOERROR) */ -#define TIF_NOERROR 12 /* Force successful syscall return */ -#define TIF_NOTIFY_RESUME 13 /* callback before returning to user */ -#define TIF_UPROBE 14 /* breakpointed or single-stepping */ -#define TIF_EMULATE_STACK_STORE 16 /* Is an instruction emulation +#define TIF_RESTORE_TM 16 /* need to restore TM FP/VEC/VSX */ +#define TIF_SINGLESTEP 17 /* singlestepping active */ +#define TIF_RESTOREALL 18 /* Restore all regs (implies NOERROR) */ +#define TIF_NOERROR 19 /* Force successful syscall return */ +#define TIF_EMULATE_STACK_STORE 20 /* Is an instruction emulation for stack store? */ -#define TIF_MEMDIE 17 /* is terminating due to OOM killer */ #if defined(CONFIG_PPC64) -#define TIF_ELF2ABI 18 /* function descriptors must die! */ +#define TIF_ELF2ABI 21 /* function descriptors must die! */ #endif -#define TIF_POLLING_NRFLAG 19 /* true if poll_idle() is polling TIF_NEED_RESCHED */ -#define TIF_32BIT 20 /* 32 bit binary */ -#define TIF_SYSCALL_RET 21 /* syscall error value set */ +#define TIF_POLLING_NRFLAG 22 /* true if poll_idle() is polling TIF_NEED_RESCHED */ +#define TIF_32BIT 23 /* 32 bit binary */ +#define TIF_SYSCALL_RET 24 /* syscall error value set */ /* as above, but as bit values */ -#define _TIF_SIGPENDING (1<