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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-369e8ec50bcsm61918825eec.23.2026.10.27.04.50.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 04:50:19 -0700 (PDT) From: Sivansh Gupta To: linux-arm-msm@vger.kernel.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, andersson@kernel.org, konradybcio@kernel.org, abelvesa@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Sivansh Gupta , Gopikrishna Garmidi Subject: [PATCH 4/4] arm64: dts: qcom: Add Mahua QCB Date: Tue, 27 Oct 2026 17:19:55 +0530 Message-ID: <20261027114955.1266499-5-sivansh.gupta@oss.qualcomm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261027114955.1266499-1-sivansh.gupta@oss.qualcomm.com> References: <20261027114955.1266499-1-sivansh.gupta@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI3MDA0NyBTYWx0ZWRfX67vWSfVO7yCW tA2Vu63OgWeZ4OCLiO/vY7zYVDif+qYmvWl10TkUjT3L17VAIA/Tx0NY2oH/Ez8UqyJQD8xQ5kP FdGiGFWcnX1K+jkYLa2WYYRq6o9ZJ3E= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI3MDA0NyBTYWx0ZWRfX2XDkQC8xEz4N ENQ4eZuoKc8yVfQDfo6s34P7j4na8+JocsyuYz/MgJGtVu5AhT3EMQl8tLyQhiZCLqo9+kM1PA/ SUTIXW2yCDus2dhmeihzGgJ8H0W/KY9LldXcJugUkJOPt5AQp4kj52umJuMGd8xvZD2wjagnt5N WWohcds/FGovzwlvxY2UgFcSniEjn/3lS3leEdLS30XPXDAPwRW2eKhLsLzvuDQ98tRN41MzgOb FMYuYn8eAzpUhh/HQ45nB0VikFUq3J0riGJayaCqDg9S0mrAA0NYackHHfEThLr2NvU+xlyyXct O8gz6jiXrniiyZ9yq2B6ZSPVr6r1ibG38b8V2Zuu0mx3Ek7EVPiDQFWzxBXkG91chR42Ur40XU/ vrfZDnBQJ8fS5jiHnUgGYKXoYqx66CQJg1z76ua2b19RKKjThxAeXRNJ0KsfsQEKOKNlELeyWbw GlKBE25Svx3TD2nXGNg== X-Proofpoint-ORIG-GUID: 4FpCED5wx5HCZJQ_NVZg3jKmRbR0PIsa X-Proofpoint-GUID: 4FpCED5wx5HCZJQ_NVZg3jKmRbR0PIsa X-Authority-Analysis: v=2.4 cv=XaIcX455 c=1 sm=1 tr=0 ts=6ae08ffe cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=Ajfpb6hXBSAmRpdWA78A:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-27_02,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 phishscore=0 spamscore=0 bulkscore=0 priorityscore=1501 clxscore=1015 lowpriorityscore=0 suspectscore=0 impostorscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610270047 Add initial device tree support for Mahua QCB. Mahua QCB is a variant of Glymur QCB but using Mahua SoC instead of Glymur SoC. Mahua is a 12 core derivative of Glymur SoC. Unlike the CRD, the QCB is suitable for compute workloads, power measurements and oscilloscope-based hardware validation. Includes glymur-qcb.dtsi, adds Mahua QCB specific board compatible, adds tcsr regulator-supply properties, removed cluster2 PMIC/thermal nodes. Co-developed-by: Gopikrishna Garmidi Signed-off-by: Gopikrishna Garmidi Signed-off-by: Sivansh Gupta --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/mahua-qcb.dts | 38 ++++++++++++++++++++++++++ 2 files changed, 39 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/mahua-qcb.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 88230c4e00ea..830c43000897 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -65,6 +65,7 @@ lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += mahua-crd.dtb dtb-$(CONFIG_ARCH_QCOM) += mahua-lenovo-thinkpad-t14s-gen7-lcd.dtb +dtb-$(CONFIG_ARCH_QCOM) += mahua-qcb.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-fairphone-fp6.dtb dtb-$(CONFIG_ARCH_QCOM) += milos-nothing-asteroids.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-arduino-monza.dtb diff --git a/arch/arm64/boot/dts/qcom/mahua-qcb.dts b/arch/arm64/boot/dts/qcom/mahua-qcb.dts new file mode 100644 index 000000000000..0c742c54a237 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/mahua-qcb.dts @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/dts-v1/; + +#include "mahua.dtsi" +#include "glymur-qcb.dtsi" + +/* PMICs tied to Glymur's cluster2 are absent on Mahua. */ +/delete-node/ &pmcx0102_d_e0; +/delete-node/ &pmcx0102_d0_thermal; +/delete-node/ &pmh0104_i_e0; +/delete-node/ &pmh0104_i0_thermal; +/delete-node/ &pmh0104_j_e0; +/delete-node/ &pmh0104_j0_thermal; + +/ { + model = "Qualcomm Technologies, Inc. Mahua QCB"; + compatible = "qcom,mahua-qcb", "qcom,mahua"; +}; + +&tcsr { + vdda-qrefrpt0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrpt3-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-qrefrpt4-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrpt5-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qrefrx0-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx1-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx2-0p9-supply = <&vreg_l2f_e1_0p83>; + vdda-qrefrx3-0p9-supply = <&vreg_l2h_e0_0p72>; + vdda-qreftx1-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen3-0p9-supply = <&vreg_l1f_e1_0p82>; + vdda-refgen3-1p2-supply = <&vreg_l4f_e1_1p08>; +}; -- 2.43.0