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Tue, 27 Oct 2026 06:21:04 -0700 (PDT) Received: from SMW032656.wbi.nxp.com ([128.77.115.158]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a35a08dcbfsm177568315e9.2.2026.10.27.06.21.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 06:21:02 -0700 (PDT) From: Laurentiu Mihalcea To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Fabio Estevam , elena.popa@nxp.com, cosmin.stoica@nxp.com Cc: Pengutronix Kernel Team , devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2] arm64: dts: imx95-navq: add USB1/USB2 nodes Date: Tue, 27 Oct 2026 15:16:30 +0200 Message-ID: <20261027131630.575-1-laurentiumihalcea111@gmail.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Laurentiu Mihalcea Add and enable the DT nodes for USB1 and USB2. Signed-off-by: Laurentiu Mihalcea --- v1 -> v2: * change USB2 DR mode to OTG to match TypeC connector configuration. The controller should actually support the software-based host <-> device switch. --- arch/arm64/boot/dts/freescale/imx95-navq.dts | 121 +++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx95-navq.dts b/arch/arm64/boot/dts/freescale/imx95-navq.dts index 7860c113e9e0..b668c752905b 100644 --- a/arch/arm64/boot/dts/freescale/imx95-navq.dts +++ b/arch/arm64/boot/dts/freescale/imx95-navq.dts @@ -5,6 +5,8 @@ /dts-v1/; +#include + #include "imx95.dtsi" / { @@ -80,6 +82,72 @@ i2c3_gpio_expander_21: gpio-expander@21 { pinctrl-0 = <&pinctrl_i2c3_gpio_expander_21>; pinctrl-names = "default"; }; + + ptn5110_usb3: tcpc@50 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x50>; + interrupt-parent = <&gpio4>; + /* USB_PTN5110_ALERT_B - shared IRQ line with tcpc@51 */ + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_typec>; + pinctrl-names = "default"; + + /* no SINK circuit (EN_SINK1 tied to TP32) */ + connector { + compatible = "usb-c-connector"; + label = "USB1 3.0 Type C"; + data-role = "dual"; + power-role = "source"; + self-powered; + source-pdos = ; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + typec1_con_hs: endpoint { + remote-endpoint = <&usb3_data_hs>; + }; + }; + + port@1 { + reg = <1>; + + typec1_con_ss: endpoint { + remote-endpoint = <&usb3_data_ss>; + }; + }; + }; + }; + }; + + ptn5110_usb2: tcpc@51 { + compatible = "nxp,ptn5110", "tcpci"; + reg = <0x51>; + interrupt-parent = <&gpio4>; + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_typec>; + pinctrl-names = "default"; + + /* no SINK circuit (EN_SINK1 tied to TP30) */ + connector { + compatible = "usb-c-connector"; + label = "USB2 2.0 Type C"; + data-role = "dual"; + power-role = "source"; + self-powered; + source-pdos = ; + + port { + typec2_con_hs: endpoint { + remote-endpoint = <&usb2_data_hs>; + }; + }; + }; + }; }; &lpuart1 { @@ -145,6 +213,10 @@ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = ; }; + pinctrl_typec: typecgrp { + fsl,pins = ; + }; + pinctrl_uart1: uart1grp { bootph-pre-ram; fsl,pins = , @@ -198,6 +270,55 @@ pinctrl_usdhc2: usdhc2grp { }; }; +&usb2 { + disable-over-current; + dr_mode = "otg"; + usb-role-switch; + + status = "okay"; + + port { + usb2_data_hs: endpoint { + remote-endpoint = <&typec2_con_hs>; + }; + }; +}; + +&usb3_dwc3 { + adp-disable; + dr_mode = "otg"; + hnp-disable; + srp-disable; + usb-role-switch; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + + status = "okay"; + + port { + usb3_data_hs: endpoint { + remote-endpoint = <&typec1_con_hs>; + }; + }; +}; + +&usb3_phy { + orientation-switch; + fsl,phy-pcs-tx-deemph-3p5db-attenuation-db = <17>; + fsl,phy-pcs-tx-swing-full-percent = <100>; + fsl,phy-tx-preemp-amp-tune-microamp = <600>; + fsl,phy-tx-vboost-level-microvolt = <1156>; + fsl,phy-tx-vref-tune-percent = <100>; + + status = "okay"; + + port { + usb3_data_ss: endpoint { + remote-endpoint = <&typec1_con_ss>; + }; + }; +}; + &usdhc1 { bootph-pre-ram; bus-width = <8>; -- 2.53.0