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Tue, 27 Oct 2026 16:06:34 +0100 From: Thomas Bourgoin To: Maxime Chevallier , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , "Alexandre Torgue" , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , "Stanislav Fomichev" , Lorenzo Bianconi , Christophe Roullier CC: , , , , , Thomas Bourgoin Subject: [PATCH 0/1] net: stmmac: descriptor management issue during PM sequence Date: Tue, 27 Oct 2026 16:05:55 +0100 Message-ID: <20261027150556.51209-1-thomas.bourgoin@foss.st.com> X-Mailer: git-send-email 2.43.0 X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: STKCAS1NODE1.st.com (10.75.128.134) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CPH1EPF0000052B:EE_|VI0PR10MB9252:EE_ X-MS-Office365-Filtering-Correlation-Id: 442827d1-4b2c-4cfd-8193-08df343be4a3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|7416014|1800799024|376014|18002099003|921020|11063799006|5023799004|56012099006|261026140227099003|261026121527099003|10067099003|261021123027099003|261021121427099003|261009223027099003|261022105027099003|261022075727099003; X-Microsoft-Antispam-Message-Info: Q8AOGHb524WH0dgoK0YGR25JcXOow18yuFWG9efVU+w8yx8qec5WQMWzerS7vlgWbkiVRp0a2X5XK4tEMs0FLy1k/TwuGDbT2jEEQlGES7d592atW/gymqr6FxNN5y+CCUN4R6gKhJOcEnkUXYV15UcxOzrONyk1v5iMB+rvawRNV3ureEf9fF0f7ovA2Yu9b+RSYz/zTnbKXew3xNfj4+ZQsm6RIuV4OIFYDRzjUGf54R1zEN7rb6HWTUp+kataBK0dwOHcnn1ZENEw4Go7ftk8AN8mw5+8CRhTiYcva5dg5FVaDnzwz3JI3MSScuMhmXeaJXpaSZk5ZG6Luch/3G3byiYPGOm7+FgbsyuEQA9UKf2h+J+xmuVJ7xc0FoepYn/rKbduNV3uQMtALZVV9TOFzQBY1ZuZNfhDwA+OZC8NdjudOPSyV6BJYwcisls+Urdu+IRn6eElH0tm4nq1puvxRA2zCsp/fiN2p9dLXiVEx1PvVkGNPqehoetLII2r4P1qun/M7eEf4soT32mHGgIKJPzIMTfDzD+ogPavgPEZ/3+uqjh60UForNC9BFchCiifTADBW266kv3kiYWmmGoMmnJxiNMblDS7TJtD1mA4O0NuQbSmdDLI+pYFLcOxVikCeVAloDwIO65Rh8FqdF4R+1UGQHL9+x3BHO4r7aXnwzY1W74Gn2/6Ce9lQ6m0ovaLgeaWYNPeA+T98GoR2ib8im8SMbJA+D+aPi+/8jwqWRkQfzogzmYd3+AVs0V8 X-Forefront-Antispam-Report: CIP:164.130.1.59;CTRY:IT;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:smtpO365.st.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(23010399003)(7416014)(1800799024)(376014)(18002099003)(921020)(11063799006)(5023799004)(56012099006)(261026140227099003)(261026121527099003)(10067099003)(261021123027099003)(261021121427099003)(261009223027099003)(261022105027099003)(261022075727099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: eBwz9OtJIdMLBgL6Vilmmm9SLSWHQave8m1/oEJ4emEKj77E39FZQSHBaxQNXU51sEQJdGaW8K0mKrAhd7kMf/rLnIkEG+oXdm8Pi+v70MaEIrttPEneltk6Glz0tA4xb2Uv81fI3Mh0Bv4+unnvCSlSE/mJfSyrZSgCmNEVPgQaEzOQ2S+XVwnkTzolG5fw1XaLA5QxaaQAr6cUPmVzQUNuhR2E5HVTKntPgBal4DNunE0dHyHcwjGp4NyBH5/1UuBoGtbPYWZr0j5j44/EpsBYms+61l7UHsbHhlY31nGNpwcjC7mLTYMvnv9+Bs086+JmpmX5AM9eJrFH1Epvd2aM02tv00CPngWqaoh24TgWMBaP99fuNWGB7qrPhVHBeJr/Ks9qgvWYYYZLP7Bs0t+aushYNo+AQ8dxc8TQSU6pvEUY7v6rPtbuIbU6AjCQ X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2026 15:06:35.2643 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 442827d1-4b2c-4cfd-8193-08df343be4a3 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.59];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: CPH1EPF0000052B.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI0PR10MB9252 Hello, During low power sequence on STM32MP21 we sometimes observe out of range access to the DDR by the GMAC ethernet. I managed to narrow down the issue to the resume sequence of the RX descriptors with the function stmmac_clear_descriptors(). On resume, stmmac_clear_descriptors() returns RX descriptors to the DMA without restoring their buffer addresses. On DWMAC4, the DMA will therefore consider a descriptor for the application as one for the DMA. This can lead to illegal access from the DMA anywhere. On STM32MP21 the DMA address bus is 40 bits, thus the extended status from the write-back descriptor is read as an high address by the DMA. DMA will then try to write in the DDR at 0x100000000 whereas on STM32MP215f-dk DDR is only 2Gb from 0x8000 0000 to 0xffff ffff and nothing is mapped at 0x100000000. All the other SoCs of the STM32MP1x or STM32MP2x are using a GMAC with a 32bits DMA address, so I do not have illegal attemps. To fix this, I propose to reconstruct the RX descriptors that have been used by the DMA but not forwarded to the NAPI function stmmac_rx() before suspend. I'm not used to this driver especially the xsk management and zero copy part. Since this driver is used by a lot of plateforms I'm open to all suggestions. This V1 propose to reuse stmmac_init_rx_buffers() but maybe using stmmac_refill() would better fit the issue. From what I read, I could not call stmmac_refill() as rx_q->cur_rx is only updated in stmmac_rx(), so stmmac_rx_dirty() returns 0. Thomas Bourgoin (1): net: stmmac: rebuild RX descriptors before restarting DMA on resume .../net/ethernet/stmicro/stmmac/stmmac_main.c | 86 +++++++++++++++---- 1 file changed, 68 insertions(+), 18 deletions(-) -- 2.43.0