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Tue, 27 Oct 2026 16:06:39 +0100 From: Thomas Bourgoin To: Maxime Chevallier , Andrew Lunn , "David S . Miller" , "Eric Dumazet" , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , "Alexandre Torgue" , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , John Fastabend , "Stanislav Fomichev" , Lorenzo Bianconi , Christophe Roullier CC: , , , , , Thomas Bourgoin Subject: [PATCH 1/1] net: stmmac: rebuild RX descriptors before restarting DMA on resume Date: Tue, 27 Oct 2026 16:05:56 +0100 Message-ID: <20261027150556.51209-2-thomas.bourgoin@foss.st.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261027150556.51209-1-thomas.bourgoin@foss.st.com> References: <20261027150556.51209-1-thomas.bourgoin@foss.st.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: STKCAS1NODE1.st.com (10.75.128.134) To STKDAG1NODE1.st.com (10.75.128.132) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MI3PEPF00008555:EE_|PAVPR10MB7114:EE_ X-MS-Office365-Filtering-Correlation-Id: 7fa953c8-89aa-483a-1538-08df343bf373 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|23010399003|376014|7416014|1800799024|18002099003|22082099003|921020|11063799006|5023799004|56012099006|261026140227099003|261021121427099003|10067099003|261021123027099003|261009221227099003|261009223327099003|261009223027099003|261009220027099003|261009221727099003|261022105027099003|261022075727099003; X-Microsoft-Antispam-Message-Info: nR9G1MpjPthTxpaMBrpvrllt/35j5VQlNeWvtr5CY2PU5ym7wivAGkawI8bF4uKwQu8MAirpcfF9+9dAyNU2S3jIHicf40ifAVphX47RhlpVlDJCMdt1dHwgAIdWN+HNJpCxjcDjA9v24uu7cOHuNLVXkCDC8z0M3dUrxP7HKYNEgD78b2QF/1yOgAG/rj6kklvjqyeydP5IK9+NOzKqlPMt6BAvaFbiMAAofYCA/9G4TqY2td29ZAy6scrH1JwaBk2TSV6YHQpKhrzSXRrTigNXbD5/OxhGr14hY+yS+yUixXFLyQsC1k25YtVvUzbQjNlXG+EOivF/ArXuQMira6elLLETcL/a3XRvsfMsiTKSSWPzcqhIUx8Hsrjl80oXgJ9TJd6oiUPnlHrFaK/5v5nJTFvarURasb1yGbHdfcfdmHEhx0vuXE4oP/NrwPCCn9FWuOXmPpWx276FupESkWvmyQxuAXfwZ1xyw8y3u5YgoFn80uxCp9iaqgsWre8ibbdlmRhvOtufAPTKO3motD+pZa7COMN33wcb2EoWHRzSgKrb1q7Jf4leehd4E5oKEI6/DA64EKNf3j2hsGi3HBd+hAQz1jZIMn28fCVhM27j4ILx9Pl7VqoTZnzfOz/z9Hr+fKXxA7W9FmICHrU0K4cfdQT2TI385HfxTgJ1R2cZHL3myP45GMsLviNmnuSE3jHqZ32BjqOkWMdBUOR+FrW3hyye1awKTboC2M7fbtUUJARNF3GTxTvEHwhOfvHA X-Forefront-Antispam-Report: CIP:164.130.1.60;CTRY:IT;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:smtpO365.st.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(23010399003)(376014)(7416014)(1800799024)(18002099003)(22082099003)(921020)(11063799006)(5023799004)(56012099006)(261026140227099003)(261021121427099003)(10067099003)(261021123027099003)(261009221227099003)(261009223327099003)(261009223027099003)(261009220027099003)(261009221727099003)(261022105027099003)(261022075727099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5rvPoeIca6UFUHYapw0CLefQRdxrC1LTwD2tG4yPW1HOE2+GhR8nF3ElIgaDamVA942qxtGeXyDhJU3cKXn+KoX78NAmH/Fpofank4Xbm9xvFSrYHAmJowyq2UGGg1pw1A6mqK0VHJCn4gwia5JVcAkM/ACmrJmO4E6tbCDjX2j3QiyIUxq3NB4Jyy2vbt5x65tuomA3l7gjcH1h15m/cq7TcsChXoLNAumnzXd3QEpyV6lz18na/7oqigD9D+SrcOoK6nWFl1blSqPUg32F+FiFoZtdNeCRFbFEp+qoUew/c6VeMNT1zVuabgBewTYZiEeLTW5gB1KgfXcu/HlON4cXLNP5YghCJB0lO4hR1itJbg1xPc0S6t/Lk99+XxVos/TptIbJbkZALTIVw5oFQ1F+byb1QLmOxxgAqncthzgJCghR2SJf1bJ416YWzbDv X-OriginatorOrg: foss.st.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2026 15:07:00.1265 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fa953c8-89aa-483a-1538-08df343bf373 X-MS-Exchange-CrossTenant-Id: 75e027c9-20d5-47d5-b82f-77d7cd041e8f X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=75e027c9-20d5-47d5-b82f-77d7cd041e8f;Ip=[164.130.1.60];Helo=[smtpO365.st.com] X-MS-Exchange-CrossTenant-AuthSource: MI3PEPF00008555.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAVPR10MB7114 An RX descriptor can be written back by the DMA before suspend without being processed by NAPI. Its buffer address fields then contain receive status rather than DMA addresses. On resume, stmmac_clear_descriptors() returns RX descriptors to the DMA without restoring their buffer addresses. On DWMAC4, the DMA will therefore consider a descriptor for the application as one for the DMA. This can lead to illegal access from the DMA anywhere. For example, on STM32MP21 the DMA address bus is 40 bits, thus the extended status from the write-back descriptor is read as an high address by the DMA. DMA will then try to write in the DDR at 0x100000000 whereas on STM32MP215f-dk DDR is only 2Gb from 0x8000 0000 to 0xffff ffff and nothing is mapped at 0x100000000. To fix this, reconstruct the entire RX ring before rearming descriptors and restarting the DMA. Reuse existing buffers, allocate missing ones, and restore their DMA addresses independently of the saved RX producer and consumer indices. Reset the queue indices only after descriptor reconstruction succeeds. Update stmmac_init_rx_buffers() to preserve an existing split-header secondary page and restore its DMA address. Fold TX buffer cleanup into the descriptor resume helper before clearing the TX descriptors. Signed-off-by: Thomas Bourgoin --- .../net/ethernet/stmicro/stmmac/stmmac_main.c | 86 +++++++++++++++---- 1 file changed, 68 insertions(+), 18 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c index 9ded31150fbe..198629265c90 100644 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c @@ -1700,8 +1700,10 @@ static int stmmac_init_rx_buffers(struct stmmac_priv *priv, buf->page_offset = stmmac_rx_offset(priv); } - if (stmmac_rx_check_buf2_cap(priv) && !buf->sec_page) { - buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, gfp); + if (stmmac_rx_check_buf2_cap(priv)) { + if (!buf->sec_page) + buf->sec_page = page_pool_alloc_pages(rx_q->page_pool, + gfp); if (!buf->sec_page) return -ENOMEM; @@ -2149,19 +2151,6 @@ static void dma_free_tx_skbufs(struct stmmac_priv *priv, } } -/** - * stmmac_free_tx_skbufs - free TX skb buffers - * @priv: private structure - */ -static void stmmac_free_tx_skbufs(struct stmmac_priv *priv) -{ - u8 tx_queue_cnt = priv->plat->tx_queues_to_use; - u8 queue; - - for (queue = 0; queue < tx_queue_cnt; queue++) - dma_free_tx_skbufs(priv, &priv->dma_conf, queue); -} - /** * __free_dma_rx_desc_resources - free RX dma desc resources (per queue) * @priv: private structure @@ -8425,6 +8414,63 @@ static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue) rx_q->dirty_rx = 0; } +static int stmmac_resume_rx_descriptors(struct stmmac_priv *priv, + struct stmmac_dma_conf *dma_conf, + u32 queue) +{ + struct stmmac_rx_queue *rx_q = &dma_conf->rx_queue[queue]; + int i; + int ret; + + for (i = 0; i < dma_conf->dma_rx_size; i++) { + struct dma_desc *p = stmmac_get_rx_desc(priv, rx_q, i); + struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i]; + dma_addr_t dma_addr; + + if (rx_q->xsk_pool) { + if (!buf->xdp) { + buf->xdp = xsk_buff_alloc(rx_q->xsk_pool); + if (!buf->xdp) + return -ENOMEM; + } + dma_addr = xsk_buff_xdp_get_dma(buf->xdp); + stmmac_set_desc_addr(priv, p, dma_addr); + stmmac_set_desc_sec_addr(priv, p, 0, false); + } else { + ret = stmmac_init_rx_buffers(priv, dma_conf, p, i, + GFP_KERNEL, queue); + if (ret) + return ret; + } + } + + return 0; +} + +static int stmmac_resume_descriptors(struct stmmac_priv *priv, + struct stmmac_dma_conf *dma_conf) +{ + u32 rx_queue_cnt = priv->plat->rx_queues_to_use; + u32 tx_queue_cnt = priv->plat->tx_queues_to_use; + u32 queue; + int ret; + + for (queue = 0; queue < rx_queue_cnt; queue++) { + ret = stmmac_resume_rx_descriptors(priv, dma_conf, queue); + if (ret) + return ret; + + stmmac_clear_rx_descriptors(priv, dma_conf, queue); + } + + for (queue = 0; queue < tx_queue_cnt; queue++) { + dma_free_tx_skbufs(priv, &priv->dma_conf, queue); + stmmac_clear_tx_descriptors(priv, dma_conf, queue); + } + + return 0; +} + static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue) { struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue]; @@ -8507,10 +8553,14 @@ int stmmac_resume(struct device *dev) mutex_lock(&priv->lock); - stmmac_reset_queues_param(priv); + ret = stmmac_resume_descriptors(priv, &priv->dma_conf); + if (ret < 0) { + netdev_err(priv->dev, "%s: Resume descriptor failed\n", + __func__); + goto error_unlock; + } - stmmac_free_tx_skbufs(priv); - stmmac_clear_descriptors(priv, &priv->dma_conf); + stmmac_reset_queues_param(priv); ret = stmmac_hw_setup(ndev); if (ret < 0) { -- 2.43.0