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Wed, 28 Oct 2026 08:54:10 -0700 (PDT) Received: from z13-ek5.local ([151.40.161.170]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4aa7f3229dbsm1468515e9.1.2026.10.28.08.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 08:54:09 -0700 (PDT) From: Ettore Chimenti Subject: [PATCH v2 0/4] clk: ti: fapll/dm816x: clock tree and calculation fixes Date: Wed, 28 Oct 2026 16:53:48 +0100 Message-Id: <20261028-patch-ektor5-dm8168-clk-v2-0-dc6bf0fabae4@linaro.org> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/3WNQQ6CMBBFr0Jm7ZgOoQRceQ/DAsoII0hJi0RDu LsF4tLlS95/fwHPTtjDJVrA8Sxe7BAgPkVg2nJoGKUODLGKU1KU4FhOpkXuJus01s+M0gxN3yE nh0C6UhDWo+O7vPfyrTjYv6oHm2nLbUYrPkQ++/VMm/d70X9fZkKFWZXnRpta64SuvQyls2frG ijWdf0Ckyt7RtEAAAA= X-Change-ID: 20261014-patch-ektor5-dm8168-clk-e426101415b0 To: Tero Kristo , Stephen Boyd , Brian Masney , Jerome Brunet , Tony Lindgren , Michael Turquette , Andrew Goodbody , Rouven Czerwinski Cc: linux-omap@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Ettore Chimenti X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1793202849; l=1986; i=ettore.chimenti@linaro.org; s=20261014; h=from:subject:message-id; bh=yKm8jdJ4eG09cLn4qLiQzmeN4+VpA6d2SRVgK0o0Pa8=; b=Dl1ClXIoZyogzSsxG3KH455rWygbMMmT04YoMPUCSMBnFY1rfcDnqhFcu7LmfqiKcD9HlwqU1 pNy/qQ0jp/HCOZXLspdK9GcqGaVHcZEzUBrIP70TxYkZE2qGxsqUua7 X-Developer-Key: i=ettore.chimenti@linaro.org; a=ed25519; pk=wCaUblFVaqhuBTQt/hAtysafsAaEsqj/yOD9SPlz6NM= During TI DM8168-EVM board testing we found that the clock hierarchy and clock calculation was broken already on 6.12: main_pll_clk1 <--- main PLL should be parent of other PLLs. sysclk1_ck main_pll_clk7 ... main_pll_clk6 ... main_pll_clk5 ... main_pll_clk4 ... This series brings fixes and additions for TI DM816x / FAPLL clock tree and frequency calculation. Summary: - Fix clock tree hierarchy by not using ti_dt_clk_name() helper, that causes the first PLL as the parent of all clocks in DM816x. - Correct rate calculation logic in fapll driver (1/2^24, was 1/10^7). - Add sys_ck alias required for DM816x clock lookup, fixing a boot error. - Add error logging for clocks failing registration to ease debugging. Fixing clock tree hierarchy is critical as it fixes DM8168-EVM boot failure in 7.3-rc7. These fixes are affecting DM816x SoCs only. Signed-off-by: Ettore Chimenti --- Changes in v2: - Fixed off-by-one error in clock calculation (Sashiko). - Fixed clock calculation also in the set rate path. - Added Fixes tag to clock calculation fix patch. - Link to v1: https://patch.msgid.link/20261015-patch-ektor5-dm8168-clk-v1-0-8b99c5cd5541@linaro.org --- Andrew Goodbody (1): clk: ti: fapll: Fix clock speed calculation Ettore Chimenti (1): clk-816x: add sys_ck clock as sys_clkin_ck alias Rouven Czerwinski (2): clk: ti: fapll: remove ti_dt_clk_name helper clk: ti: fapll: print clock name that fails to register drivers/clk/ti/clk-816x.c | 1 + drivers/clk/ti/fapll.c | 22 +++++++++------------- 2 files changed, 10 insertions(+), 13 deletions(-) --- base-commit: d135ab453a7400a34930bdda1ef4bdc8acfac80e change-id: 20261014-patch-ektor5-dm8168-clk-e426101415b0 Best regards, -- Ettore Chimenti