From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=5.135.140.105 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793150028; b=q+8jcFEfx1pV+FoK1elAPc8kB6tps5p9kchrW5JQSCfz0Kno1no7Xyi0MLgq1s7xuOA2 uQFUz7TX+y3wSfCRq4XqtvIbpKBqOUbWoSem3BHqkPGH7WctRkE5U0Y/8wGP03nbyLPve lGOxLrWMVEfQwYjdkhRYneRxPpUhgC2yfv8yUjhLoF+4e80C359SsjzR1QgSfDTfwLzrO FSQMTcmBtWBeGpSQkJM/w0oZXgk9RgbMuRofTk3LKysyV6M8dPJ1cXFJjdBD/3pHDoVKo lzsQHorLYZZQ3+GGFOdJe1j/R+KbP2hMJGLmkl8V4rmMYZ4JdPM4aVWajIn+sTfKPoQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793150028; h=DMARC-Filter:Received:DKIM-Signature:From:To:Cc:Subject:Date: Message-Id:MIME-Version:Content-Transfer-Encoding: X-Last-TLS-Session-Version; bh=lLmtu+5/W2Rqcj5M+1JbfEqak1TRlWcazl6OlaI9MjQ=; b=YZ8ERl6gH2OeiUGaVl8IF1LHMEkDxb5btiGLVM5Qtm0xsK7Yyl0tPkQ8rMFdNQmg6/by C9XnXnaowGUtBCDiOyRJW5pG8T8hoG8kM2h6Sil52lq3m1HangcBr4dabc21D+ATKzaQn 8ROe8y63spxkV0f2/c70x8RP5t4gAyAXvkM67/KNFqjzaS2t9UG258v2h8KnDfuN0X5zD TOww9HrOQuxfFXxTCwZQEPWmnOZoHCt3gHAxsXiiaoF7/z+iHS2ulL3nDQR6bSV0SDDdN HrGMaw3whrcZIz3r80QgEuaLvta+2Uol8C7EISrxS9og/by+UOXdn1HsD8En5cSmQvg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=cjdns.fr; spf=none smtp.mailfrom=cjdns.fr; dkim=pass header.d=cjdns.fr header.i=@cjdns.fr header.a=rsa-sha256 header.s=dkim header.b="tWTRG/IS"; arc=none smtp.remote-ip=5.135.140.105 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D1B5D606A31E; Wed, 28 Oct 2026 01:13:47 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org D1B5D606A31E Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=cjdns.fr header.i=@cjdns.fr header.a=rsa-sha256 header.s=dkim header.b=tWTRG/IS Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id A557E14893A; Wed, 28 Oct 2026 02:13:23 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1793150017; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding; bh=lLmtu+5/W2Rqcj5M+1JbfEqak1TRlWcazl6OlaI9MjQ=; b=tWTRG/ISeKkRPUGx/qKAyPTeBrg3mKS+zt2GZ9uEQfCz5EFCWyVxCIeNf71kYU9vyE3aYc dCw5cx/4gkTJJbWfPM368b6//FQQd678sv9qmBhgJdM/2NQfVo8SNatfV8Tx49OLJSzODR e4LesBYQkZaEQNdAqKKdbpIt0jvLlykUb5+CfozNW4uORlcRAAVFYcyq4cDL6Hjcbz172a FGZ01IkaZCASCikneRtbEExMzAeNvO9rYONOqcOIaHd0VXl8wc5zjmBvYWmtIJ/2HSvuRy ofbB1l2jN7XdXSGO7Q1qx68DMsNZUdPPXiATpjmEPvwlKDberfmURoHWsUruvA== From: Caleb James DeLisle To: netdev@vger.kernel.org Cc: andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chester.a.unal@arinc9.com, daniel@makrotopia.org, linux@armlinux.org.uk, arinc.unal@arinc9.com, Landen.Chao@mediatek.com, dqfext@gmail.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, naseefkm@gmail.com, b.larsson@gmx.com, Caleb James DeLisle Subject: [PATCH v3 0/7] net: dsa: mt7530: support EcoNet EN751221 Date: Wed, 28 Oct 2026 01:13:10 +0000 Message-Id: <20261028011317.1557238-1-cjd@cjdns.fr> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 The EcoNet EN751221 has a unique switch configuration. Every chip made with an EN751221 die has at least one on-die MT7530 that is MMIO based. This switch has 3x 10/100 ports and 1x gigabit port. Some popular chip packages such as the EN7513G and EN7526G have another MT7530 implemented as a multi-chip-module that connects to port 5 of the on-die switch and is controlled via the MDIO controller integrated in the on-die MT7530. In this configurations, the upstream switch is put into a "passthrough" mode in which all traffic is forwarded between port 5 and port 6 without altering its DSA tags. Furthermore, since the DSA core does not call mt753x_setup until all switches are present, and the downstream switch only becomes available when the upstream switch has configured its MDIO controller, the MDIO controller setup on MMIO implementations must be done before mt753x_setup, or else it will never complete. Finally, the on-die switch and the MCM switch connect via a TRGMII link which requires calibration. In order to calibrate this, PLL adjustment must be possible on the on-die switch, necessitating changes to the core_(set|clear|write|rmw) functions to support MMIO implementations. Solve all of these issues, add the TRGMII calibration, and add support for both switches. Since this patchset will probably be subject to some discussion, please consider accepting any patches that are non-controversial since it will make future re-submissions easier. Thanks! Changes since v2: * The MCM switch previously identified as econet,en751221, similarly to mediatek,mt7621, however since econet,en751221 is already used for the SoC compatible, is it changed to econet,en751221-gswitch. The name "gswitch" is chosen as there's apparently no standard and for EN751221 this is intuitive because it is the gigabit switch used in implementations with a "G" in the chip name. * Do not use a special mt7530_switch_ops for passthrough mode, instead detect passthrough mode in each function and exit early so as to avoid errors when trying to make a configuration switch-tree wide. Changes since v1: * Move mt7530_setup_mdio_irq out of mt7530_setup_mdio because mt7530_setup_mdio may be called before mt753x_setup * Do not return error in mt7988_probe if mt7530_setup_mdio fails because doing so leaks the DSA switch registration, and in any case mt7530_setup_mdio will be called again. * default_taps_ondie not being used en751221_trgmii_cal_ok unused args * Use clk_drvp / clk_drvp instead of drvp / drvn (typo) * en751221_set_tx_drive ext values too large for fields - values taken from reference implementation, reduced from 16 to 15. v1: https://lore.kernel.org/netdev/20260909140346.2861572-1-cjd@cjdns.fr/ Caleb James DeLisle (7): net: dsa: mt7530: get ctrl phy addr using a function dt-bindings: net: dsa: mediatek,mt7530: add passthrough mode net: dsa: mediatek: add support for passthrough mode net: dsa: mediatek: support PLL setup on MMIO MT7530 net: dsa: mediatek: support MDIO switch downstream of MMIO switch dt-bindings: net: dsa: mediatek,mt7530: add econet,en751221 net: dsa: mediatek: support EN751221 switch .../bindings/net/dsa/mediatek,mt7530.yaml | 50 +- drivers/net/dsa/mt7530-mdio.c | 1 + drivers/net/dsa/mt7530-mmio.c | 10 +- drivers/net/dsa/mt7530.c | 609 ++++++++++++++++-- drivers/net/dsa/mt7530.h | 46 +- 5 files changed, 663 insertions(+), 53 deletions(-) base-commit: 734bef548a96e8774d6eef5dfa2026c6edc4e80b -- 2.39.5