From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=5.135.140.105 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793150037; b=zIfIU9BDh/lRzCJN5fAMx62irleY3pfq4FfHd7q4+aJs4vr2wlZX4FYykyWX6qImoUAR 6MzREiDSQOWvXrWPjS0pk/riKowEiu1/CD4fYcVNneFmy8m44gCHC6jnKOre77Qe5v5FX tL+hcbnrYCX+fnPM3t/HLw/g+0i1btQLcbeCrBgBcKmzPr970hy34ejJdhqUotvRHiM3x pfKKE6FFJgNKcxw2nMC0+c2IjPhDTdvIWTVHAlunFdnM7IZhzbkCgvonsgjZZu9sbfHsy XclmMNEV2hMue9I5s9ufSMslsxIX7RBlXen1fVzX+lf0iyJgxNkK7SrLQ6hTKvDKuPA== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793150037; h=DMARC-Filter:Received:DKIM-Signature:From:To:Cc:Subject:Date: Message-Id:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding:X-Last-TLS-Session-Version; bh=ADqrrJvW23LFM0pGXYZQATdOejQwocht4yhLCBcfUYY=; b=imdxINmpFX3+cbAbvuXRcssl1v4VthY5FDGLlFtSsYYoHOwT2vsOMyddbZjM/joP1zp1 PRbHAcqrjDmLXvI33nBICBfu5jIp8Vi/fsnCqMPmtmPtJFvKIc4a3MIXAFKMDo7SI5FOX 4QUWQz+pzaQygMUgfikJ6klg+W8Rmeo4pTamMWG/KahnXyijB6CWPltmx2vc2pqzgr0+2 4liNfjMXLQESa6drt2EReTyvDmpsNCUh5GXa1JwoFzpmu3kPTVDIL2fe6nwG57oi2se6W ldavEmit2ij69JNn/n4xODSzvFX2Dm0NmF7xjH0mqvkRnEF7UjjXVaXqv0AcmbgOAhg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=cjdns.fr; spf=pass smtp.mailfrom=cjdns.fr; dkim=pass header.d=cjdns.fr header.i=@cjdns.fr header.a=rsa-sha256 header.s=dkim header.b=VDUTHKoW; arc=none smtp.remote-ip=5.135.140.105 Received: from mail.cjdns.fr (mail.cjdns.fr [5.135.140.105]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E28BA606A324; Wed, 28 Oct 2026 01:13:56 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org E28BA606A324 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cjdns.fr Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key, unprotected) header.d=cjdns.fr header.i=@cjdns.fr header.a=rsa-sha256 header.s=dkim header.b=VDUTHKoW Received: from [127.0.0.1] (localhost [127.0.0.1]) by localhost (Mailerdaemon) with ESMTPSA id D88FB1497AB; Wed, 28 Oct 2026 02:13:50 +0100 (CET) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cjdns.fr; s=dkim; t=1793150034; h=from:subject:date:message-id:to:cc:mime-version: content-transfer-encoding:in-reply-to:references; bh=ADqrrJvW23LFM0pGXYZQATdOejQwocht4yhLCBcfUYY=; b=VDUTHKoWLkmSLXIbTOCCmtykkplv8++xjvmWBHVbWRu7BG/coDf6i3CR33yr/VhxkNkJZr jCtfrO7SGQ2DCRhVpN4oY7++rz8tQyBvNf2FruzXFEAqrkepxlCwg7Bupumk2AqQK61NLJ xTajaQrdN9bmD9zABy8/nqMqoN9YeZ8ctMRSbIxXZzD2vuk8xQGCtC1HgzP1TVb8SldAw3 aZ0+hWruelRT+zbWff5c2OG4f94zP5pgwokdcYZqdTbgyQWFwHycS6u3MOduBcn+S4ZRSu asaSbo9A0Q2Zq8oNiorR9f1FpTYXs1eWck0vFOWPvnq8y6SvfVYeez83EnJphg== From: Caleb James DeLisle To: netdev@vger.kernel.org Cc: andrew@lunn.ch, olteanv@gmail.com, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, chester.a.unal@arinc9.com, daniel@makrotopia.org, linux@armlinux.org.uk, arinc.unal@arinc9.com, Landen.Chao@mediatek.com, dqfext@gmail.com, sean.wang@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, naseefkm@gmail.com, b.larsson@gmx.com, Caleb James DeLisle Subject: [PATCH v3 4/7] net: dsa: mediatek: support PLL setup on MMIO MT7530 Date: Wed, 28 Oct 2026 01:13:14 +0000 Message-Id: <20261028011317.1557238-5-cjd@cjdns.fr> In-Reply-To: <20261028011317.1557238-1-cjd@cjdns.fr> References: <20261028011317.1557238-1-cjd@cjdns.fr> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Last-TLS-Session-Version: TLSv1.3 On MT7530 and MT7531, PHYs are an integral part of the switch. However, on MT7530, certain configuration such as PLL setup is done via special registers on one of the PHYs. In an MMIO implementation, the MDIO bus is part of the switch itself. This bus is already setup for PHY calibration so begin using it for core switch PLL setup. Signed-off-by: Caleb James DeLisle --- drivers/net/dsa/mt7530.c | 15 +++++++++++++++ drivers/net/dsa/mt7530.h | 4 ++++ 2 files changed, 19 insertions(+) diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mt7530.c index 3eb2e11d6985..d09ff207e2df 100644 --- a/drivers/net/dsa/mt7530.c +++ b/drivers/net/dsa/mt7530.c @@ -77,6 +77,12 @@ core_write(struct mt7530_priv *priv, u32 reg, u32 val) struct mii_bus *bus = priv->bus; int ret; + if (!bus) + bus = priv->child_bus; + + if (WARN_ON_ONCE(!bus)) + return; + mt7530_mutex_lock(priv); /* Write the desired MMD Devad */ @@ -112,6 +118,12 @@ core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) u32 val; int ret; + if (!bus) + bus = priv->child_bus; + + if (WARN_ON_ONCE(!bus)) + return; + mt7530_mutex_lock(priv); /* Write the desired MMD Devad */ @@ -2472,8 +2484,11 @@ mt7530_setup_mdio(struct mt7530_priv *priv) if (priv->irq_domain && !mnp) mt7530_setup_mdio_irq(priv); + priv->child_bus = bus; + ret = devm_of_mdiobus_register(dev, bus, mnp); if (ret) { + priv->child_bus = NULL; dev_err(dev, "failed to register MDIO bus: %d\n", ret); if (priv->irq_domain && !mnp) mt7530_free_mdio_irq(priv); diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mt7530.h index 108c831dd012..5b7394f6383c 100644 --- a/drivers/net/dsa/mt7530.h +++ b/drivers/net/dsa/mt7530.h @@ -886,6 +886,9 @@ struct mt753x_info { * @dev: The device pointer * @ds: The pointer to the dsa core structure * @bus: The bus used for the device and built-in PHY + * @child_bus: The bus created by the device, on MDIO implementations + * this is bus indirectly accesses `bus`, on MMIO + * implementations this bus is part of the switch. * @regmap: The regmap instance representing all switch registers * @rstc: The pointer to reset control used by MCM * @core_pwr: The power supplied into the core @@ -914,6 +917,7 @@ struct mt7530_priv { struct device *dev; struct dsa_switch *ds; struct mii_bus *bus; + struct mii_bus *child_bus; struct regmap *regmap; struct reset_control *rstc; struct regulator *core_pwr; -- 2.39.5