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([2804:5d20:6009:6701:4df:52dc:4559:394e]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5ec4f9210c3sm403450e0c.8.2026.10.27.19.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 19:19:31 -0700 (PDT) From: Stephan Costa Barros To: Mike Looijmans Cc: Jonathan Cameron , David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Shevchenko , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Krzysztof Kozlowski , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 2/6] iio: adc: ti-ads1298: fix power-up and clock handling Date: Tue, 27 Oct 2026 23:19:15 -0300 Message-ID: <20261028021915.29695-1-stephanbrrs8@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <184780c8-6d87-4983-8399-6e509a250cfc@topic.nl> References: <20261024231335.280955-1-stephanbrrs8@gmail.com> <20261024231335.280955-3-stephanbrrs8@gmail.com> <184780c8-6d87-4983-8399-6e509a250cfc@topic.nl> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hi Mike, On Mon, Oct 26, 2026 at 07:27:22AM +0100, Mike Looijmans wrote: > On 25-10-2026 01:13, Stephan Costa Barros wrote: > > - The datasheet powers up the supplies first, then the clock, then > > waits t_POR = 2^18 clock cycles (128 ms at 2.048 MHz) before the > > reset. The driver enabled an external clock and the vref supply > > before AVDD, reset right away, and did not wait for the 150 ms > > start-up of the internal reference. Follow the datasheet. Probe takes > > about 280 ms longer. > > The driver followed the correct procedure: Keep reset asserted until the > power is enabled. > > We've seen the chips misbehave when the power supplies ramp up > erratically. Keeping them in reset until the power supplies are stable > solves that issue, if a reset signal is available. The driver is based > on real experience with these chips. Thanks, that experience is what I lack here. The patch keeps that: RESET is still requested asserted before anything is enabled, and released only after AVDD, VREF and the clock are on. What changes is that AVDD now comes before the clock and VREF, and that the driver waits t_POR before releasing RESET. "reset right away" meant releasing it without that wait; I'll reword it. Is AVDD before the clock fine with you? Section 11.1 asks to keep all digital inputs, CLK included, low until the supplies are stable. > There is no need to wait for the internal reference startup. The > internal reference only affects the ADC performance, it isn't required > for digital communication. By the time userspace gets to use the driver, > those 150 ms will have passed already. Agreed, I'll drop that wait. > We actually have 8 (or more) of these chips on a single board. If it > takes 8x 280 ms extra to boot such a board, it will fail to meet medical > specs (reboot in 5 seconds). Understood. Without the reference wait it is t_POR alone, 128 ms per chip at 2.048 MHz, still about 1 s for 8 chips probed one after another. > The ADS1298 datasheet says "18" clock cycles, not "2^18". Quite a > difference. We would definitely have noticed if the reset timeout was > that far off. I read 2^18 in the current revision, SBAS459K (August 2015), Table 38: "t_POR, Wait after power up until reset, MIN 2^18 t_CLK", with the note "When using an external clock, t_POR timing does not start until CLK is valid". Its revision history lists "Changed power-up reset wait time in Table 38", so older revisions may differ. The 18 t_CLK in Figure 105 is the wait after the reset pulse, which the driver already does. The ADS1299 datasheet (SBAS499C, Table 30) gives 2^18 t_CLK as well. That said, I have not seen the missing wait cause a failure on hardware. On my board the supplies are up long before the driver probes, so t_POR has passed by then, and that may be the case on yours too. Does the driver switch the supplies on your boards, or are they on from boot? In v3 the supply order, the t_POR wait and the clock rate become separate patches, as Jonathan asked, so each can be judged on its own. Regards, Stephan