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([2804:5d20:6009:6701:4df:52dc:4559:394e]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5ec4f8dfcf1sm415927e0c.3.2026.10.27.19.22.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 19:22:44 -0700 (PDT) From: Stephan Costa Barros To: Jonathan Cameron Cc: David Lechner , =?UTF-8?q?Nuno=20S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mike Looijmans , Andy Shevchenko , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , Krzysztof Kozlowski , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/6] iio: adc: ti-ads1298: prepare for more chip families Date: Tue, 27 Oct 2026 23:22:36 -0300 Message-ID: <20261028022236.30455-1-stephanbrrs8@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261025232608.06a5762c@jic23-hlaptop> References: <20261024231335.280955-1-stephanbrrs8@gmail.com> <20261024231335.280955-5-stephanbrrs8@gmail.com> <20261025232608.06a5762c@jic23-hlaptop> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On Sun, 25 Oct 2026 23:26:08 +0000, Jonathan Cameron wrote: > > +/* What differs between the chip families the driver supports */ > > This is very standard naming and purpose. I'd drop the comment. Will drop it, and the other generic ones. dr and hr will be spelled out, and vref_mv becomes internal_vref_mV. > > + /* CONFIG3 has the VREF_4V bit, which selects a 4 V internal reference */ > > + bool has_vref_4v; > > I'm lost here. If it's about the bit, then name it after the bit. > I suspect it's about internal reference that can be disabled or not? > In that case can you name it for that functionality instead? > > From a quick look below, seems it is about what of two modes can be > used? If so how does that fit with just one vref_mv above? It is about the internal reference. On the ADS129x it is 2.4 V, or 4 V when CONFIG3 VREF_4V is set, which the driver does when AVDD is 4.4 V or more. On the ADS1299 it is a fixed 4.5 V, and that bit is reserved. So vref_mv was the default internal reference, and has_vref_4v said that the 4 V option exists. For v3: chip info has internal_vref_mV (2400 and 4500) and a bool named for the 4 V option; init chooses the reference once and keeps it, so read_raw no longer reads CONFIG3. Andy asked for the same. > > + /* Reserved bits of CONFIG3 that must be written as 1 */ > > This one is interesting. Normally we deal with these by just using > RMW cycles on such a register. Can we do that here? Yes. CONFIG3 resets to 40h on the ADS129x and 60h on the ADS1299, with the reserved bits set, and the regmap has no defaults, so regmap_update_bits() reads them from the chip. config3_reserved goes. > Please use FIELD_GET() and fix the family masks to be values in the field > rather than the shifted version. You might want to do that > as a separate precursor patch. Looks like there may be other similar > changes in driver around fields vs value defines. Will do Thanks, Stephan