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Tue, 27 Oct 2026 22:01:26 -0700 (PDT) Received: from localhost.localdomain (dynamic-2a02-3100-a45b-7d01-5035-b393-698f-53f0.310.pool.telefonica.de. [2a02:3100:a45b:7d01:5035:b393:698f:53f0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94eb8a60fsm13523365e9.3.2026.10.27.22.01.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 27 Oct 2026 22:01:25 -0700 (PDT) From: Karl Mehltretter To: Marc Zyngier , Oliver Upton Cc: Karl Mehltretter , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Eric Auger , Paolo Bonzini , Sean Christopherson , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 0/3] KVM: arm64: Preserve level IRQ re-pending Date: Wed, 28 Oct 2026 06:01:10 +0100 Message-Id: <20261028050113.10046-1-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit A guest can set a level interrupt pending again while handling it. The GIC records Active and Pending and delivers the interrupt after deactivation. KVM instead drops the second pending state for both the GICv2 and GICv3 backends. The VGIC keeps software pending state outside the LR because commit 67b5b673ad4d stopped placing Pending and Active together for level interrupts. When the LR is folded, KVM cannot distinguish the pending state used to populate the LR from a later ISPENDR write. Synchronize the target vCPU's LRs in vgic_mmio_write_spending() with vgic_access_active_prepare() and vgic_access_active_finish() under config_lock before setting pending_latch, as suggested by Oliver Upton. When a vCPU writes its own GICR_ISPENDR0, this synchronization is a no-op. For shared interrupts or remote redistributor writes, stopping the guest folds any prior ack from the target vCPU's LRs before the new pending state is recorded. In the v2 and v3 fold paths, clear pending_latch when an LR populated for an inactive interrupt no longer reports a pending state, and preserve a latch written while the interrupt was active. The last patch adds a two-vCPU GICv3 selftest covering same-vCPU and cross-vCPU re-pending while active, as well as a cross-vCPU ISPENDR write before the ack. The issue was reproduced with Zephyr, NuttX and RT-Thread test harnesses that configure an unused SPI as level-sensitive, pend it via GICD_ISPENDR, and re-pend it once from the ISR before deactivation. On a Raspberry Pi 400 host with a GIC-400, each GICv2 guest handled the SPI once on the baseline and twice with the RFC fix. A native RT-Thread run on the same GIC-400 also delivered the re-pended interrupt. The v2 change was A/B tested with RT-Thread's direct and mailbox-pic reproducers on Linux/KVM hosts running under QEMU TCG with GICv2 and GICv3. The baseline lost the second event and v2 delivered it. The new GICv3 selftest also passes in that setup. I do not have a physical GICv3 host, so the GICv3 testing is emulated. Changes in v2: - Synchronize target vCPU LRs in vgic_mmio_write_spending() via vgic_access_active_prepare() and vgic_access_active_finish() under config_lock instead of tracking on-LR writes with a separate latch_written flag (Oliver Upton). - Extend the selftest to verify that a cross-vCPU GICD_ISPENDR write before the ack merges with the initial pending state without causing a second delivery. - Drop RFC prefix. - Link to v1: https://lore.kernel.org/r/20261022064628.4206-1-kmehltretter@gmail.com Karl Mehltretter (3): KVM: arm64: vgic-v2: Don't drop pending writes to active level IRQs KVM: arm64: vgic-v3: Don't drop pending writes to active level IRQs KVM: selftests: arm64: Test pending writes to active level IRQs arch/arm64/kvm/vgic/vgic-mmio.c | 76 +++++----- arch/arm64/kvm/vgic/vgic-v2.c | 10 +- arch/arm64/kvm/vgic/vgic-v3.c | 10 +- tools/testing/selftests/kvm/arm64/vgic_irq.c | 140 +++++++++++++++++++ 4 files changed, 197 insertions(+), 39 deletions(-) base-commit: dd0bc00e3e9201fd49b62ff9cc07890c89003afe -- 2.39.5 (Apple Git-154)