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[2a02:3100:a45b:7d01:5035:b393:698f:53f0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a94eb8a60fsm13523365e9.3.2026.10.27.22.01.30 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 27 Oct 2026 22:01:31 -0700 (PDT) From: Karl Mehltretter To: Marc Zyngier , Oliver Upton Cc: Karl Mehltretter , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Mark Rutland , Eric Auger , Paolo Bonzini , Sean Christopherson , Shuah Khan , linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] KVM: selftests: arm64: Test pending writes to active level IRQs Date: Wed, 28 Oct 2026 06:01:13 +0100 Message-Id: <20261028050113.10046-4-kmehltretter@gmail.com> X-Mailer: git-send-email 2.39.5 (Apple Git-154) In-Reply-To: <20261028050113.10046-1-kmehltretter@gmail.com> References: <20261028050113.10046-1-kmehltretter@gmail.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add a two-vCPU GICv3 test for a level SPI set pending through GICD_ISPENDR. Re-pend the interrupt while it is active, first from the handling vCPU and then from the other vCPU. Require a second delivery after deactivation in both cases. Also check that the other vCPU observes the initial pending state before the interrupt is acknowledged, and that a remote GICD_ISPENDR write before the ack merges with the initial pending state without causing a second delivery. Without the VGIC fix, the pending state written while active is cleared on deactivation and the test fails before the second delivery. Assisted-by: LLM Signed-off-by: Karl Mehltretter --- tools/testing/selftests/kvm/arm64/vgic_irq.c | 140 +++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/tools/testing/selftests/kvm/arm64/vgic_irq.c b/tools/testing/selftests/kvm/arm64/vgic_irq.c index 3cb85932ee85c..83091e0384c22 100644 --- a/tools/testing/selftests/kvm/arm64/vgic_irq.c +++ b/tools/testing/selftests/kvm/arm64/vgic_irq.c @@ -959,6 +959,145 @@ static void guest_code_timer_spi(struct test_args *args, int cpuid) GUEST_DONE(); } +#define REPEND_READ 1 +#define REPEND_READ_DONE 2 +#define REPEND_WRITE 3 +#define REPEND_PRE_ACK 4 +#define REPEND_PRE_ACK_DONE 5 + +/* + * A level-sensitive SPI that is set pending through GICD_ISPENDR stays + * pending for every vCPU until it is acked. If it is set pending again while + * it is active, it becomes active and pending and must be taken a second time + * once it has been deactivated. The second pending state comes from the vCPU + * that handles the interrupt in the first round, and from the other vCPU in + * the second. A remote GICD_ISPENDR write before the interrupt is acked merges + * with the initial pending state without causing a second delivery. + */ +static void guest_code_level_repend(struct test_args *args, int cpuid) +{ + int i; + + gic_init(GIC_V3, 2); + + gic_set_eoi_split(1); + gic_set_priority_mask(CPU_PRIO_MASK); + + if (cpuid == 0) { + u32 intid; + + local_irq_disable(); + + gic_irq_set_config(MIN_SPI, false); + gic_set_priority(MIN_SPI, IRQ_DEFAULT_PRIO); + gic_irq_enable(MIN_SPI); + + for (i = 0; i < 2; i++) { + gic_irq_set_pending(MIN_SPI); + + if (i == 1) { + /* Not acked yet: the other vCPU sees it pending */ + WRITE_ONCE(args->shared_data, REPEND_READ); + dsb(ishst); + + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) != REPEND_READ_DONE); + } + + GUEST_ASSERT(gic_irq_get_pending(MIN_SPI)); + intid = wait_for_and_activate_irq(); + GUEST_ASSERT_EQ(intid, MIN_SPI); + + if (i == 0) { + gic_irq_set_pending(MIN_SPI); + } else { + WRITE_ONCE(args->shared_data, REPEND_WRITE); + dsb(ishst); + + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) == REPEND_WRITE); + } + + GUEST_ASSERT(gic_irq_get_active(MIN_SPI)); + gic_set_eoi(intid); + gic_set_dir(intid); + isb(); + + /* The second pending state must not have been lost */ + GUEST_ASSERT(gic_irq_get_pending(MIN_SPI)); + intid = wait_for_and_activate_irq(); + GUEST_ASSERT_EQ(intid, MIN_SPI); + + gic_set_eoi(intid); + gic_set_dir(intid); + isb(); + + GUEST_ASSERT(!gic_irq_get_active(MIN_SPI)); + GUEST_ASSERT(!gic_irq_get_pending(MIN_SPI)); + GUEST_ASSERT_EQ(gic_get_and_ack_irq(), IAR_SPURIOUS); + } + + /* + * A remote ISPENDR write before the interrupt is acked merges + * with the initial pending state and must not cause a second + * delivery after deactivation. + */ + gic_irq_set_pending(MIN_SPI); + + WRITE_ONCE(args->shared_data, REPEND_PRE_ACK); + dsb(ishst); + + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) != REPEND_PRE_ACK_DONE); + + GUEST_ASSERT(gic_irq_get_pending(MIN_SPI)); + intid = wait_for_and_activate_irq(); + GUEST_ASSERT_EQ(intid, MIN_SPI); + + gic_set_eoi(intid); + gic_set_dir(intid); + isb(); + + GUEST_ASSERT(!gic_irq_get_active(MIN_SPI)); + GUEST_ASSERT(!gic_irq_get_pending(MIN_SPI)); + GUEST_ASSERT_EQ(gic_get_and_ack_irq(), IAR_SPURIOUS); + } else { + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) != REPEND_READ); + + for (i = 0; i < 64; i++) + GUEST_ASSERT(gic_irq_get_pending(MIN_SPI)); + + WRITE_ONCE(args->shared_data, REPEND_READ_DONE); + dsb(ishst); + + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) != REPEND_WRITE); + + gic_irq_set_pending(MIN_SPI); + + WRITE_ONCE(args->shared_data, 0); + dsb(ishst); + + do { + dsb(ishld); + } while (READ_ONCE(args->shared_data) != REPEND_PRE_ACK); + + GUEST_ASSERT(gic_irq_get_pending(MIN_SPI)); + gic_irq_set_pending(MIN_SPI); + + WRITE_ONCE(args->shared_data, REPEND_PRE_ACK_DONE); + dsb(ishst); + } + + GUEST_DONE(); +} + static void *test_vcpu_run(void *arg) { struct kvm_vcpu *vcpu = arg; @@ -1073,6 +1212,7 @@ int main(int argc, char **argv) test_vgic_two_cpus(guest_code_asym_dir); test_vgic_two_cpus(guest_code_group_en); test_vgic_two_cpus(guest_code_timer_spi); + test_vgic_two_cpus(guest_code_level_repend); } else { test_vgic(nr_irqs, level_sensitive, eoi_split); } -- 2.39.5 (Apple Git-154)