From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=209.85.221.46 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1793173485; b=DbuAJjuFGdOwfv4S1nEDIaakSrVx8UFAd22X+8nRlgvE9N4zcrKPfYYXd1v2pTogfVD1 vu33TbSshxeFJspFhgY79n5+KMGq7+ETlU3GeVu84tsZtZRwIZQ2R3LGpR/lBspQZUEg6 eKzGqcg8NkzSd3+/0IWnzorbcXFQoh0LKSNm8SwK4AFdgtm0PjxuKSQY6+XyRDV/2W6C+ gOz68wTr9a0ysa2m0GCNsxpUlg+LSrYbF358ZZRaqVmV4ZES/OIY2DMCQEPt4QwwxymLB o1bMRswSpbaiqU01BrRwS+4NBi6PCgleuCtpKlI0CEVhzq4WwouB/dpb2jOej3N2/Ig== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1793173485; h=DMARC-Filter:Received:DKIM-Signature:X-Google-DKIM-Signature: X-Gm-Message-State:X-Gm-Gg:X-Received:Received:From:To:Cc:Subject: Date:Message-ID:X-Mailer:In-Reply-To:References:MIME-Version: Content-Transfer-Encoding; bh=Iye3U/dlGnZ00j+zjr7HAr1TeijBnNq2JkuJKGfJwwY=; b=kdaiibCDTptbEuBW0vWNZvpgY4mOnudPQJBalDZaRb0aNZgiH7YNedmxmbc838PCI1C1 +R1keyBq7l5HpT4tmRQA1unYKPDKRZx8XogfCtOVuz12VYQd+jQkIWqZ1X2CR0BF/1FL+ 1Ke6+XrmND0PIxGj+nk38wMeG+sgv2AbcTwdwGMj+PapWcILe5K8x5kOC0ZDz2sHMSaUc wQT2APvzGsrUYAFv0KUqsaY8Ai5AnOLAhdPLwLX6joEkIAOZg/dnOmPCgR+gD/0xhuoqJ FWYEJwEgsNlrpU73m+DlzyQkVNBLoeePh+pRDidutihFFwrgbJGMuUREhuaUPJniIDA== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass header.from=amarulasolutions.com; spf=pass smtp.mailfrom=amarulasolutions.com; dkim=pass header.d=amarulasolutions.com header.i=@amarulasolutions.com header.a=rsa-sha256 header.s=google header.b=eUFPTEYu; arc=none smtp.remote-ip=209.85.221.46 Received: from mail-wr1-f46.google.com (mail-wr1-f46.google.com [209.85.221.46]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 05886606A32F for ; Wed, 28 Oct 2026 07:44:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 05886606A32F Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=amarulasolutions.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key, unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.a=rsa-sha256 header.s=google header.b=eUFPTEYu Received: by mail-wr1-f46.google.com with SMTP id ffacd0b85a97d-48dfc0421d9so501992f8f.1 for ; Wed, 28 Oct 2026 00:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1793173483; x=1793778283; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to:content-type; bh=Iye3U/dlGnZ00j+zjr7HAr1TeijBnNq2JkuJKGfJwwY=; b=eUFPTEYuWWk3vbc9XWvlH2BlVk7sDoYniIKaACUAPTVadYzh2YiOHwL9bC4PjTkxKv Qwucdi8AvUdnGNgB1Ox8sV01tCXYu8QotrE3MdyjPCUp8ezCPwq/ZbELSt1/+eipXh9T PUrmWBOjntU+YFYIfkWzgSM1IF41jHTSxwAFM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20260707; t=1793173483; x=1793778283; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to:content-type; bh=Iye3U/dlGnZ00j+zjr7HAr1TeijBnNq2JkuJKGfJwwY=; b=tQST4tAKj2nByo7DxzETtyR3Q9G6pj9HQm1GJiTnl7aXTEnrFUI8yxBB25rWu1K7d4 StwOBoqI1GSCTRyXppMguUBkHjECeQdMhIiac95V19nbnrJT7g/xHwtDzwxv+f/MSi3I Z98NIrabZjxEShZPbWK/hmK9uwenAkpETF9zr4I6QnIcftszrQ+kmz7dbXAYDnjQD3We W7YYits6E+MNXPP8Vg/1diYNf40UCkYPAMIzAkoYpb7crZEEZKe7dvDhQx14i4fTHFzq pqQgwIyxVIZ4W3e5IxnyS/BCJ9EgtDheoFYT9H5iLe8/lA9AWDwtre4sISPC5OOfoWph jT9g== X-Gm-Message-State: AFq9FYI3ciythOgZTTF1fdZk+F9hKP01NukIgG8fJoX6iNPhSLvRNmfu ZsuTRR1Jslvx2fNbtMZ2N7DLApR/ehGAvxEwUCfKrg5mfA9nw8U8nNeYNjgN5g5gTZsRcfjOol/ c2QeL X-Gm-Gg: AYBFou3SQmuloiLYT0+EgoakD0T2wmSxyJRfEJ3Rlzbp+tKtc0We+/EKfrnVNjtMTQf +YEHv8OSS4P9M+WtfXGj3UEkFDiEf/GZpmamntgwFe3k2SSHsvllxk/xYPTLJpUavCk/UwxjitV DtzaYKfZtSsqlBm/hMqQXoOVc0GUFgzoVkC4veaGdafo4hwZeleLYY0fOUUiSGwFjMYWTQVIAzR D3HdTVIyh334Y76Rb89drL5Ro+qWg4ar6ai4pB+wZWr+OoiyzPgalSNZ46oLmGgbmg6v55+UeZ9 YWh/kkbYKA01P4xiA1Sp66ZErJbyX+VoWfplb9GGZar3sYzazCeWXtb53zIVye582+zcFysRNR4 EVeaLUtLblVykq6Zz8nAswjrYtHYwqHnCK2GeKq11chYbYbMgeo3QvqrgoxjrXQzmsf+/F4m39V oLPGrLgLAH721uWwoPN5mC0AGE70fqZZs44BCC1UGNsutDf5r3IyIAPWOMX+xdyhtl3F1lvp6wc N6rmkSssAi1nekvCngB7LJYoHFXwXqQz+aFt2q4AYsC371kPjtPXRW1WYZprEvR2owBHrpwmVJr SHJ9VgxKC3L3qA/KgpGaOLV3STMnianHcrsFk9zoqS/TAgtAclc7AIn+4snKpC1CiGbFNOLTZTq tHeB3t4OpqfCjLDMjePOuSa1/8VbBN0VmLPTwGdgXrft3tjODWfekp94oIWQ5PhpYqOBssfW3F/ hZLumzIxalyyiRd5WlVHElfiwMmg== X-Received: by 2002:a5d:4f07:0:b0:48c:7ee3:e07d with SMTP id ffacd0b85a97d-48e5d312c2bmr2716635f8f.52.1793173483413; Wed, 28 Oct 2026 00:44:43 -0700 (PDT) Received: from dario-ThinkPad-P14s-Gen-5.homenet.telecomitalia.it (host-79-14-29-58.business.telecomitalia.it. [79.14.29.58]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e412cc164sm25324882f8f.7.2026.10.28.00.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 Oct 2026 00:44:42 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: linux-amarula@amarulasolutions.com, michael@amarulasolutions.com, Dario Binacchi , Brian Masney , Jerome Brunet , Stephen Boyd , Tero Kristo , linux-clk@vger.kernel.org, linux-omap@vger.kernel.org Subject: [PATCH v3 2/3] clk: ti: dpll: use the generic spread spectrum configuration Date: Wed, 28 Oct 2026 08:44:08 +0100 Message-ID: <20261028074436.1958132-3-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261028074436.1958132-1-dario.binacchi@amarulasolutions.com> References: <20261028074436.1958132-1-dario.binacchi@amarulasolutions.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The clock framework provides a generic API and DT property for spread spectrum clocking (SSC) since commit c86814e70390 ("clk: Introduce clk_hw_set_spread_spectrum"). Implement the set_spread_spectrum callback and convert the deprecated vendor specific properties to the generic configuration, so that existing DTs keep working. The SSC registers are programmed at the next rate change, as with the vendor specific properties. The generic framework expresses the spread in permyriad rather than permille, hence the change in the deltaM step computation, and also supports up-spread, which is rejected as the hardware does not support it. Signed-off-by: Dario Binacchi --- Changes in v3: - Keep parsing the deprecated vendor specific properties drivers/clk/ti/clock.h | 2 ++ drivers/clk/ti/dpll.c | 20 +++++++++---- drivers/clk/ti/dpll3xxx.c | 61 ++++++++++++++++++++++++++++++++------- include/linux/clk/ti.h | 9 ++---- 4 files changed, 70 insertions(+), 22 deletions(-) diff --git a/drivers/clk/ti/clock.h b/drivers/clk/ti/clock.h index d5e24fe4ae3a..83225e506314 100644 --- a/drivers/clk/ti/clock.h +++ b/drivers/clk/ti/clock.h @@ -271,6 +271,8 @@ int omap3_noncore_dpll_set_rate_and_parent(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate, u8 index); +int omap3_noncore_dpll_set_spread_spectrum(struct clk_hw *hw, + const struct clk_spread_spectrum *ss_conf); int omap3_noncore_dpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req); int omap2_dpll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req); diff --git a/drivers/clk/ti/dpll.c b/drivers/clk/ti/dpll.c index e01272cd628d..1329b4bc02f0 100644 --- a/drivers/clk/ti/dpll.c +++ b/drivers/clk/ti/dpll.c @@ -51,6 +51,7 @@ static const struct clk_ops dpll_ck_ops = { .set_parent = &omap3_noncore_dpll_set_parent, .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, .determine_rate = &omap3_noncore_dpll_determine_rate, + .set_spread_spectrum = &omap3_noncore_dpll_set_spread_spectrum, .get_parent = &omap2_init_dpll_parent, .save_context = &omap3_noncore_dpll_save_context, .restore_context = &omap3_noncore_dpll_restore_context, @@ -63,6 +64,7 @@ static const struct clk_ops dpll_no_gate_ck_ops = { .set_parent = &omap3_noncore_dpll_set_parent, .set_rate_and_parent = &omap3_noncore_dpll_set_rate_and_parent, .determine_rate = &omap3_noncore_dpll_determine_rate, + .set_spread_spectrum = &omap3_noncore_dpll_set_spread_spectrum, .save_context = &omap3_noncore_dpll_save_context, .restore_context = &omap3_noncore_dpll_restore_context }; @@ -278,6 +280,7 @@ static void __init of_ti_dpll_setup(struct device_node *node, struct dpll_data *dd = NULL; int ssc_clk_index; u8 dpll_mode = 0; + u32 ssc_modfreq = 0, ssc_deltam = 0; u32 min_div; dd = kmemdup(ddt, sizeof(*dd), GFP_KERNEL); @@ -349,11 +352,18 @@ static void __init of_ti_dpll_setup(struct device_node *node, &dd->ssc_modfreq_reg)) goto cleanup; - of_property_read_u32(node, "ti,ssc-modfreq-hz", - &dd->ssc_modfreq); - of_property_read_u32(node, "ti,ssc-deltam", &dd->ssc_deltam); - dd->ssc_downspread = - of_property_read_bool(node, "ti,ssc-downspread"); + /* Deprecated, superseded by assigned-clock-sscs */ + of_property_read_u32(node, "ti,ssc-modfreq-hz", &ssc_modfreq); + of_property_read_u32(node, "ti,ssc-deltam", &ssc_deltam); + if (ssc_modfreq && ssc_deltam) { + dd->ssc_conf.modfreq_hz = ssc_modfreq; + /* permille to permyriad */ + dd->ssc_conf.spread_bp = ssc_deltam * 10; + if (of_property_read_bool(node, "ti,ssc-downspread")) + dd->ssc_conf.method = CLK_SPREAD_DOWN; + else + dd->ssc_conf.method = CLK_SPREAD_CENTER; + } } if (of_property_read_bool(node, "ti,low-power-stop")) diff --git a/drivers/clk/ti/dpll3xxx.c b/drivers/clk/ti/dpll3xxx.c index 8c51b988a04f..634fe0a1f9fd 100644 --- a/drivers/clk/ti/dpll3xxx.c +++ b/drivers/clk/ti/dpll3xxx.c @@ -295,30 +295,32 @@ static void _lookup_sddiv(struct clk_hw_omap *clk, u8 *sd_div, u16 m, u8 n) * omap3_noncore_dpll_ssc_program - set spread-spectrum clocking registers * @clk: struct clk * of DPLL to set * - * Enable the DPLL spread spectrum clocking if frequency modulation and - * frequency spreading have been set, otherwise disable it. + * Enable the DPLL spread spectrum clocking according to the configuration + * set by omap3_noncore_dpll_set_spread_spectrum(), otherwise disable it. */ static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk) { struct dpll_data *dd = clk->dpll_data; + const struct clk_spread_spectrum *conf = &dd->ssc_conf; + bool downspread = conf->method == CLK_SPREAD_DOWN; unsigned long ref_rate; u32 v, ctrl, mod_freq_divider, exponent, mantissa; u32 deltam_step, deltam_ceil; ctrl = ti_clk_ll_ops->clk_readl(&dd->control_reg); - if (dd->ssc_modfreq && dd->ssc_deltam) { + if (conf->method != CLK_SPREAD_NO) { ctrl |= dd->ssc_enable_mask; - if (dd->ssc_downspread) + if (downspread) ctrl |= dd->ssc_downspread_mask; else ctrl &= ~dd->ssc_downspread_mask; ref_rate = clk_hw_get_rate(dd->clk_ref); mod_freq_divider = - (ref_rate / dd->last_rounded_n) / (4 * dd->ssc_modfreq); - if (dd->ssc_modfreq > (ref_rate / 70)) + (ref_rate / dd->last_rounded_n) / (4 * conf->modfreq_hz); + if (conf->modfreq_hz > (ref_rate / 70)) pr_warn("clock: SSC modulation frequency of DPLL %s greater than %ld\n", __clk_get_name(clk->hw.clk), ref_rate / 70); @@ -337,9 +339,10 @@ static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk) v |= exponent << __ffs(dd->ssc_modfreq_exp_mask); ti_clk_ll_ops->clk_writel(v, &dd->ssc_modfreq_reg); - deltam_step = dd->last_rounded_m * dd->ssc_deltam; - deltam_step /= 10; - if (dd->ssc_downspread) + /* spread_bp is in permyriad, convert to percent first */ + deltam_step = dd->last_rounded_m * conf->spread_bp; + deltam_step /= 100; + if (downspread) deltam_step /= 2; deltam_step <<= __ffs(dd->ssc_deltam_int_mask); @@ -353,7 +356,7 @@ static void omap3_noncore_dpll_ssc_program(struct clk_hw_omap *clk) if (deltam_step & dd->ssc_deltam_frac_mask) deltam_ceil++; - if ((dd->ssc_downspread && + if ((downspread && ((dd->last_rounded_m - (2 * deltam_ceil)) < 20 || dd->last_rounded_m > 2045)) || ((dd->last_rounded_m - deltam_ceil) < 20 || @@ -682,6 +685,44 @@ int omap3_noncore_dpll_set_rate(struct clk_hw *hw, unsigned long rate, return ret; } +/** + * omap3_noncore_dpll_set_spread_spectrum - set the DPLL SSC configuration + * @hw: pointer to the clock to set the spread spectrum configuration for + * @ss_conf: spread spectrum configuration + * + * Stores the spread spectrum clocking (SSC) configuration of the DPLL. The + * configuration is programmed along with the DPLL multiplier and divider + * at the next rate change. The hardware supports center-spread and + * down-spread only. Returns 0 on success, or a negative error value on + * failure. + */ +int omap3_noncore_dpll_set_spread_spectrum(struct clk_hw *hw, + const struct clk_spread_spectrum *ss_conf) +{ + struct clk_hw_omap *clk = to_clk_hw_omap(hw); + struct dpll_data *dd = clk->dpll_data; + + if (!dd || !dd->ssc_enable_mask) + return -EOPNOTSUPP; + + switch (ss_conf->method) { + case CLK_SPREAD_NO: + break; + case CLK_SPREAD_CENTER: + case CLK_SPREAD_DOWN: + if (!ss_conf->modfreq_hz || !ss_conf->spread_bp) + return -EINVAL; + break; + default: + /* Up-spread is not supported by the hardware */ + return -EINVAL; + } + + dd->ssc_conf = *ss_conf; + + return 0; +} + /** * omap3_noncore_dpll_set_rate_and_parent - set rate and parent for a DPLL clock * @hw: pointer to the clock to set rate and parent for diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h index 54a3fa370004..107056120c2c 100644 --- a/include/linux/clk/ti.h +++ b/include/linux/clk/ti.h @@ -65,10 +65,7 @@ struct clk_omap_reg { * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in * @control_reg - * @ssc_modfreq: the DPLL SSC frequency modulation in kHz - * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent) - * @ssc_downspread: require the only low frequency spread of the DPLL in SSC - * mode + * @ssc_conf: the DPLL SSC configuration * @flags: DPLL type/features (see below) * * Possible values for @flags: @@ -124,9 +121,7 @@ struct dpll_data { u32 ssc_modfreq_exp_mask; u32 ssc_enable_mask; u32 ssc_downspread_mask; - u32 ssc_modfreq; - u32 ssc_deltam; - bool ssc_downspread; + struct clk_spread_spectrum ssc_conf; u8 flags; }; -- 2.43.0